Modelagem de máquina de indução trifásica sem mancais com bobinado dividido

This work presents a model of bearingless induction machine with divided winding. The main goal is to obtain a machine model to use a simpler control system as used in conventional induction machine and to know its behavior. The same strategies used in conventional machines were used to reach the bearingless induction machine model, which has made possible an easier treatment of the involved parameters. The studied machine is adapted from the conventional induction machine, the stator windings were divided and all terminals had been available. This method does not need an auxiliary stator winding for the radial position control which results in a more compact machine. Another issue about this machine is the variation of inductances array also present in result of the rotor displacement. The changeable air-gap produces variation in magnetic flux and in inductances consequently. The conventional machine model can be used for the bearingless machine when the rotor is centered, but in rotor displacement condition this model is not applicable. The bearingless machine has two sets of motor-bearing, both sets with four poles. It was constructed in horizontal position and this increases difficulty in implementation. The used rotor has peculiar characteristics; it is projected according to the stator to yield the greatest torque and force possible. It is important to observe that the current unbalance generated by the position control does not modify the machine characteristics, this only occurs due the radial rotor displacement. The obtained results validate the work; the data reached by a supervisory system corresponds the foreseen results of simulation which verify the model veracity

Contribuição para o estudo do embarque de uma rede neural artificial em field programmable gate array (FPGA)

This study shows the implementation and the embedding of an Artificial Neural Network (ANN) in hardware, or in a programmable device, as a field programmable gate array (FPGA). This work allowed the exploration of different implementations, described in VHDL, of multilayer perceptrons ANN. Due to the parallelism inherent to ANNs, there are disadvantages in software implementations due to the sequential nature of the Von Neumann architectures. As an alternative to this problem, there is a hardware implementation that allows to exploit all the parallelism implicit in this model. Currently, there is an increase in use of FPGAs as a platform to implement neural networks in hardware, exploiting the high processing power, low cost, ease of programming and ability to reconfigure the circuit, allowing the network to adapt to different applications. Given this context, the aim is to develop arrays of neural networks in hardware, a flexible architecture, in which it is possible to add or remove neurons, and mainly, modify the network topology, in order to enable a modular network of fixed-point arithmetic in a FPGA. Five synthesis of VHDL descriptions were produced: two for the neuron with one or two entrances, and three different architectures of ANN. The descriptions of the used architectures became very modular, easily allowing the increase or decrease of the number of neurons. As a result, some complete neural networks were implemented in FPGA, in fixed-point arithmetic, with a high-capacity parallel processing