28 resultados para Depuração : Circuitos integrados
em Universidade Federal do Rio Grande do Norte(UFRN)
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Abstract
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In this work, the transmission line method is explored on the study of the propagation phenomenon in nonhomogeneous walls with finite thickness. It is evaluated the efficiency and applicability of the method, considering materials like gypsum, wood and brick, found in the composition of the structures of walls in question. The results obtained in this work are compared to those available in the literature, for several particular cases. A good agreement is observed, showing that the performed analysis is accurate and efficient in modeling, for instance, the wave propagation through building walls and integrated circuit layers in mobile communication and radar system applications. Later, simulations of resistive sheets devices such as Salisbury screens and Jaumann absorbers and of transmission lines made of metal-insulator-semiconductor (MIS) are made. Thereafter, it is described a study on frequency surface selective structures (FSS). It is proposed the development of devices and microwave integrated circuits (MIC) of such structures, for the accomplishment of experiments. Finally, future works are suggested, for instance, on the development of reflectarrays, frequency selective surfaces with dissimilar elements, and coupled frequency selective surfaces with elements located on different layers
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Low voltage solar panels increase the reliability of solar panels due to reduction of in series associations the configurations of photovoltaic cells. The low voltage generation requires DCDC converters devices with high efficiency, enabling raise and regulate the output voltage. This study analyzes the performance of a photovoltaic panel of Solarex, MSX model 77, configured to generate an open circuit voltage of 10.5 V, with load voltage of 8.5 V, with short circuit current of 9 A and a power of 77 W. The solar panel was assembled in the isolated photovoltaic system configuration, with and without energy storage as an interface with a DCDC converter, Booster topology. The converter was designed and fabricated using SMD (Surface Mounted Devices) technology IC (integrated circuit) that regulates its output voltage at 14.2 V, with an efficiency of 87% and providing the load a maximum power of 20.88 W. The system was installed and instrumented for measurement and acquisition of the following data: luminosities, average global radiation (data of INPE Instituto Nacional de Pesquisas Espaciais), solar panel and environment temperatures, solar panel and DC-DC converter output voltages, panel, inverter, and battery charge output currents. The photovoltaic system was initially tested in the laboratory (simulating its functioning in ideal conditions of operation) and then subjected to testing in real field conditions. The panel inclination angle was set at 5.5°, consistent with the latitude of Natal city. Factors such as climatic conditions (simultaneous variations of temperature, solar luminosities and ra diation on the panel), values of load resistance, lower limit of the maximum power required by the load (20.88 W) were predominant factors that panel does not operate with energy efficiency levels greater than 5 to 6%. The average converter efficiency designed in the field test reached 95%
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The increasingly request for processing power during last years has pushed integrated circuit industry to look for ways of providing even more processing power with less heat dissipation, power consumption, and chip area. This goal has been achieved increasing the circuit clock, but since there are physical limits of this approach a new solution emerged as the multiprocessor system on chip (MPSoC). This approach demands new tools and basic software infrastructure to take advantage of the inherent parallelism of these architectures. The oil exploration industry has one of its firsts activities the project decision on exploring oil fields, those decisions are aided by reservoir simulations demanding high processing power, the MPSoC may offer greater performance if its parallelism can be well used. This work presents a proposal of a micro-kernel operating system and auxiliary libraries aimed to the STORM MPSoC platform analyzing its influence on the problem of reservoir simulation
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The increasing complexity of integrated circuits has boosted the development of communications architectures like Networks-on-Chip (NoCs), as an architecture; alternative for interconnection of Systems-on-Chip (SoC). Networks-on-Chip complain for component reuse, parallelism and scalability, enhancing reusability in projects of dedicated applications. In the literature, lots of proposals have been made, suggesting different configurations for networks-on-chip architectures. Among all networks-on-chip considered, the architecture of IPNoSys is a non conventional one, since it allows the execution of operations, while the communication process is performed. This study aims to evaluate the execution of data-flow based applications on IPNoSys, focusing on their adaptation against the design constraints. Data-flow based applications are characterized by the flowing of continuous stream of data, on which operations are executed. We expect that these type of applications can be improved when running on IPNoSys, because they have a programming model similar to the execution model of this network. By observing the behavior of these applications when running on IPNoSys, were performed changes in the execution model of the network IPNoSys, allowing the implementation of an instruction level parallelism. For these purposes, analysis of the implementations of dataflow applications were performed and compared
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The great interest observed in wireless communication systems has required the development of new configurations of microstrip antennas, because they are easily built and integrated to other microwave circuit components, which is suitable for the construction and development of planar antenna arrays and microwave integrated circuits. This work presents a new configuration of tapered microstrip antenna, which is obtained by impressing U-slots on the conducting patch combined with a transmission line matching circuit that uses an inset length. It is shown that the use of U-slots in the microstrip antenna conducting patch excites new resonating modes, that gives a multiband characteristic for the slotted microstrip antenna, that is suitable for applications in communication systems that operates several frequencies simultaneously. Up to this date, the works reported in the literature deals with the use of Uslotted microstrip rectangular antennas fed by a coaxial probe. The properties of a linear array of microstrip patch tapered antennas are also investigated. The main parameters of the U slotted tapered microstrip antennas are investigated for different sizes and locations of the slots impressed on the conducting patch. The analysis of the proposed antenna is performed by using the resonant cavity and equivalent transmission line methods, in combination with a parametric study, that is conducted by the use of the Ansoft Designer, a commercial computer aided microwave software well known by its accuracy and efficiency. The mentioned methods are used to evaluate the effect in the antennas parameters, like resonant frequency and return loss, produced by variations of the antenna structural parameters, accomplished separately or simultaneously. An experimental investigation is also developed, that consists of the design, construction and measurement of several U slotted microstrip antenna prototypes. Finally, theoretical and simulated results are presented that are in agreement with the measured ones. These results are related to the resonating modes identification and to the determination of the main characteristics of the investigated antennas, such as resonant frequency, return loss, and radiation pattern
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This work deals with the research and development of a Pulse Width Programmable Gain Integrating Amplifier. Two Pulse Width Programmable Gain Amplifier architectures are proposed, one based on discrete components and another based on switched capacitors. From the operating requirements defined for the study, parameters are defined and simulations are carried out to validate the architecture. Subsequently, the circuit and the software are developed and tested. It is performed the evaluation of the circuits regarding the two proposed architectures, and from that, an architecture is selected to be improved, aiming the development of an integrated circuit in a future work.
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The continuous evolution of integrated circuit technology has allowed integrating thousands of transistors on a single chip. This is due to the miniaturization process, which reduces the diameter of wires and transistors. One drawback of this process is that the circuit becomes more fragile and susceptible to break, making the circuit more susceptible to permanent faults during the manufacturing process as well as during their lifetime. Coarse Grained Reconfigurable Architectures (CGRAs) have been used as an alternative to traditional architectures in an attempt to tolerate such faults due to its intrinsic hardware redundancy and high performance. This work proposes a fault tolerance mechanism in a CGRA in order to increase the architecture fault tolerance even considering a high fault rate. The proposed mechanism was added to the scheduler, which is the mechanism responsible for mapping instructions onto the architecture. The instruction mapping occurs at runtime, translating binary code without the need for recompilation. Furthermore, to allow faster implementation, instruction mapping is performed using a greedy module scheduling algorithm, which consists of a software pipeline technique for loop acceleration. The results show that, even with the proposed mechanism, the time for mapping instructions is still in order of microseconds. This result allows that instruction mapping process remains at runtime. In addition, a study was also carried out mapping scheduler rate. The results demonstrate that even at fault rates over 50% in functional units and interconnection components, the scheduler was able to map instructions onto the architecture in most of the tested applications.
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The Artificial Neural Networks (ANN), which is one of the branches of Artificial Intelligence (AI), are being employed as a solution to many complex problems existing in several areas. To solve these problems, it is essential that its implementation is done in hardware. Among the strategies to be adopted and met during the design phase and implementation of RNAs in hardware, connections between neurons are the ones that need more attention. Recently, are RNAs implemented both in application specific integrated circuits's (Application Specific Integrated Circuits - ASIC) and in integrated circuits configured by the user, like the Field Programmable Gate Array (FPGA), which have the ability to be partially rewritten, at runtime, forming thus a system Partially Reconfigurable (SPR), the use of which provides several advantages, such as flexibility in implementation and cost reduction. It has been noted a considerable increase in the use of FPGAs for implementing ANNs. Given the above, it is proposed to implement an array of reconfigurable neurons for topologies Description of artificial neural network multilayer perceptrons (MLPs) in FPGA, in order to encourage feedback and reuse of neural processors (perceptrons) used in the same area of the circuit. It is further proposed, a communication network capable of performing the reuse of artificial neurons. The architecture of the proposed system will configure various topologies MLPs networks through partial reconfiguration of the FPGA. To allow this flexibility RNAs settings, a set of digital components (datapath), and a controller were developed to execute instructions that define each topology for MLP neural network.
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The Artificial Neural Networks (ANN), which is one of the branches of Artificial Intelligence (AI), are being employed as a solution to many complex problems existing in several areas. To solve these problems, it is essential that its implementation is done in hardware. Among the strategies to be adopted and met during the design phase and implementation of RNAs in hardware, connections between neurons are the ones that need more attention. Recently, are RNAs implemented both in application specific integrated circuits's (Application Specific Integrated Circuits - ASIC) and in integrated circuits configured by the user, like the Field Programmable Gate Array (FPGA), which have the ability to be partially rewritten, at runtime, forming thus a system Partially Reconfigurable (SPR), the use of which provides several advantages, such as flexibility in implementation and cost reduction. It has been noted a considerable increase in the use of FPGAs for implementing ANNs. Given the above, it is proposed to implement an array of reconfigurable neurons for topologies Description of artificial neural network multilayer perceptrons (MLPs) in FPGA, in order to encourage feedback and reuse of neural processors (perceptrons) used in the same area of the circuit. It is further proposed, a communication network capable of performing the reuse of artificial neurons. The architecture of the proposed system will configure various topologies MLPs networks through partial reconfiguration of the FPGA. To allow this flexibility RNAs settings, a set of digital components (datapath), and a controller were developed to execute instructions that define each topology for MLP neural network.
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Considering the fact that, the use of wireless communication systems has grown too fast, investigations concerning absorbers of electromagnetic waves has called closer attention of researchers. It is applicable from indoor systems to military applications. Paralleling with this growth, some extremely relevant investigations through Frequency Selective Surfaces (FSS) allows its filter property to be applicable in several systems, for example: reflector antennas, band-pass radomes, and absorbers, which are the main objective of this work. Therefore, the main goal of this work concerns to design micro-waves absorbers through FSS. Thus, the methodology consists basically in two steps: the first step concerns a theoretical and numerical analysis of the structures involved in the process of absorption, the second step, the analysis of the cascaded structures. In order to carry out the analysis, the Equivalent Circuit Method will be used. This method provides characteristics of transmission from the structure, for a plane wave incidence and it requires an extremely limited computing resource in relation if compared to full wave analyses method. Hence, it is useful to allow fast predictions of the development of the structures. Furthermore, a spreading matrix will be used in order to cascade the conductive FSS and the resistive FSS achieving absorption characteristics in the designed band. The experimental results used for the analysis are found in the literature due to the difficulty of building soon, given that it is not a simple construction technique. To conclude, a mathematical development through the Equivalent Circuit Method of a FSS modeling with cross-dipole geometry and a resistive FSS will be presented, as well as the cascading involving the two structures. The same setting is used with a square loop geometry. Besides it, the next steps will be discussed in the conclusion.
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RAMOS, A. S. M.; OLIVEIRA, M. A. Fatores de sucesso na implementação de sistemas integrados de gestão empresarial (ERP): estudo de caso em uma média empresa. In: ENCONTRO NACIONAL DE ENGENHARIA DE PRODUÇÂO, 22., 2002, Curitiba-PR. Anais... Porto Alegre-RS: ABEPRO, 2002. v. 1.
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The IT capability is a organizational ability to perform activities of this role more effectively and an important mechanism in creating value. Its building process (stages of creation and development) occurs through management initiatives for improvement in the performance of their activities, using human resources and IT assets complementary responsible for the evolution of their organizational routines. This research deals with the IT capabilities related to SIG (integrated institutional management systems), built and deployed in UFRN (Universidade Federal do Rio Grande do Norte) to realization and control of administrative, academic and human resources activities. Since 2009, through cooperative agreements with federal and educational institutions of direct administration, UFRN has supported the implementation of these systems, currently involving more than 30 institutions. The present study aims to understand how IT capabilities, relevant in the design, implementation and dissemination of SIG, were built over time. This is a single case study of qualitative and longitudinal nature, performed by capturing, coding and analysis from secondary data and from semi-structured interviews conducted primarily with members of Superintenência de Informática, organizational unit responsible for SIG systems in UFRN. As a result, the technical, of internal relationship and external cooperation capabilities were identified as relevant in the successful trajectory of SIG systems, which have evolved in different ways. The technical capacity, initiated in 2004, toured the stages of creation and development until it reached the stage of stability in 2013, due to technological limits. Regarding the internal relationship capability, begun in 2006, it toured the stages of creation and development, having extended its scope of activities in 2009, being in development since then. Unlike the standard life cycle observed in the literature, the external cooperation capability was initiated by an intensity of initiatives and developments in the routines in 2009, which were decreasing to cease in 2013 in order to stabilize the technological infrastructure already created for cooperative institutions. It was still identified the start of cooperation in 2009 as an important event selection, responsible for changing or creating trajectories of evolution in all three capacities. The most frequent improvements initiatives were of organizational nature and the internal planning activity has been transformed over the routines of the three capabilities. Important resources and complementary assets have been identified as important for the realization of initiatives, such as human resources technical knowledge to the technical capabilities and external cooperation, and business knowledge, for all of them, as well as IT assets: the iproject application for control of development processes, and the document repository wiki. All these resources and complementary assets grew along the capacities, demonstrating its strategic value to SINFO/UFRN
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This study presents a description of the development model of a representation of simplified grid applied in hybrid load flow for calculation of the voltage variations in a steady-state caused by the wind farm on power system. Also, it proposes an optimal load-flow able to control power factor on connection bar and to minimize the loss. The analysis process on system, led by the wind producer, it has as base given technician supplied by the grid. So, the propose model to the simplification of the grid that allows the necessity of some knowledge only about the data referring the internal network, that is, the part of the network that interests in the analysis. In this way, it is intended to supply forms for the auxiliary in the systematization of the relations between the sector agents. The model for simplified network proposed identifies the internal network, external network and the buses of boulders from a study of vulnerability of the network, attributing them floating liquid powers attributing slack models. It was opted to apply the presented model in Newton-Raphson and a hybrid load flow, composed by The Gauss-Seidel method Zbarra and Summation Power. Finally, presents the results obtained to a developed computational environment of SCILAB and FORTRAN, with their respective analysis and conclusion, comparing them with the ANAREDE
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This work presents a theoretical, numerical and computation analysis of parameters of a rectangular microstrip antenna with metamaterial substrate, fin line as a coupler and also integrated devices like integrated filter antenna. It is applied theory to full-wave of Transverse Transmission Line - TTL method, to characterize the magnitude of the substrate and obtain the general equations of the electromagnetic fields. About the metamaterial, they are characterized by permittivity and permeability tensor, reaching to the general equations for the electromagnetic fields of the antenna. It is presented a study about main representation of PBG(Photonic Band Gap) material and its applied for a specific configuration. A few parameters are simulated some structures in order to reduce the physical dimensions and increase the bandwidth. The results are presented through graphs. The theoretical and computational analysis of this work have shown accurate and relatively concise. Conclusions are drawn and suggestions for future work