4 resultados para 291603 Input, Output and Data Devices

em Universidade Federal do Rio Grande do Norte(UFRN)


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This work is part of the research group studying agribusiness chains, by characterizing agroindustrial chain of cashew nuts in Rio Grande do Norte, with special emphasis on Sertão de Apodi Citizenship Territory, showing their different flows and linkages and analyzes generating jobs and income in the production of this good, from the experience of COOPAPI, using as a methodology for analyzing the input-output matrix. And this is justified by the fact that Brazil is in the context as the world's fifth largest producer of cashew nuts and the production of this product focus in the Northeast, especially the Rio Grande do Norte, which is the second largest producer of region, behind only the state of Ceará, which is the largest producer in the country. Moreover, in recent years the state has increased its insertion in international markets this product, particularly the Mossoró-Assu Territory, which constitutes the largest producer in the state, particularly the municipality of Serra do Mel, which has an arrangement different yield, based on the model of integrated rural development, embodied in family farming. Nevertheless, the Sertão de Apodi Citizenship appear as the fourth among the Citizenship territories of Rio Grande do Norte in the ranking of the production of cashew nuts, but the prevailing model of Cooperatives in the Territory, based on the Solidarity Economy, i,e, different from the old cooperative, which is based on the precepts as patronage, with cooperative owners, favor, etc.., encourages scientific research. In this, after a careful analysis of data from field research, it was noticed that among the links in the chain, the production link is what generates the most jobs, while the processing link commands to generate income, but a portion meaningful occupations and income are generated outside the territory, especially out of state RN, denouncing the gap in supply of some specific demands within the chain

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The strengthening of the domestic industry in Brazil required the modernization, mechanization and expansion of salt production. Thereafter the production of sea salt started to be made in a process of continuous flow, where the product is constantly stored in yards, with daily movements in and out of salt. Thus far, the major bottleneck found in this production process is the control of production, because due to the large amount produced and variety of losses existing in the various stages of production there are not a regulated and safe way to control inventories with accuracy and speed demanded. In a typical case with a salt marsh company of Rio Grande do Norte state, salt produced is stored in two open courtyards and inventory control of salt made by carrying input / output relationship of salt in each storage yard. This work developed a conceptual model of inventory control, based on topography, adopting surveys into one of the courtyards of the company. There were 25 biweekly survey measurements over a year book to generate digital models representing the stock. For each measurement, results were compared with the values of inventory accounting provided by the salt marsh in order to identify existing losses and mark out the sales department on the actual stock available at each measurement date. Inventories calculated by the model indicated losses of 6,349 tonnes for the period of one year book and 3,279 tonnes for the period between harvests, when compared to the accounting control

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It bet on the next generation of computers as architecture with multiple processors and/or multicore processors. In this sense there are challenges related to features interconnection, operating frequency, the area on chip, power dissipation, performance and programmability. The mechanism of interconnection and communication it was considered ideal for this type of architecture are the networks-on-chip, due its scalability, reusability and intrinsic parallelism. The networks-on-chip communication is accomplished by transmitting packets that carry data and instructions that represent requests and responses between the processing elements interconnected by the network. The transmission of packets is accomplished as in a pipeline between the routers in the network, from source to destination of the communication, even allowing simultaneous communications between pairs of different sources and destinations. From this fact, it is proposed to transform the entire infrastructure communication of network-on-chip, using the routing mechanisms, arbitration and storage, in a parallel processing system for high performance. In this proposal, the packages are formed by instructions and data that represent the applications, which are executed on routers as well as they are transmitted, using the pipeline and parallel communication transmissions. In contrast, traditional processors are not used, but only single cores that control the access to memory. An implementation of this idea is called IPNoSys (Integrated Processing NoC System), which has an own programming model and a routing algorithm that guarantees the execution of all instructions in the packets, preventing situations of deadlock, livelock and starvation. This architecture provides mechanisms for input and output, interruption and operating system support. As proof of concept was developed a programming environment and a simulator for this architecture in SystemC, which allows configuration of various parameters and to obtain several results to evaluate it

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The use of Multiple Input Multiple Output (MIMO) systems has permitted the recent evolution of wireless communication standards. The Spatial Multiplexing MIMO technique, in particular, provides a linear gain at the transmission capacity with the minimum between the numbers of transmit and receive antennas. To obtain a near capacity performance in SM-MIMO systems a soft decision Maximum A Posteriori Probability MIMO detector is necessary. However, such detector is too complex for practical solutions. Hence, the goal of a MIMO detector algorithm aimed for implementation is to get a good approximation of the ideal detector while keeping an acceptable complexity. Moreover, the algorithm needs to be mapped to a VLSI architecture with small area and high data rate. Since Spatial Multiplexing is a recent technique, it is argued that there is still much room for development of related algorithms and architectures. Therefore, this thesis focused on the study of sub optimum algorithms and VLSI architectures for broadband MIMO detector with soft decision. As a result, novel algorithms have been developed starting from proposals of optimizations for already established algorithms. Based on these results, new MIMO detector architectures with configurable modulation and competitive area, performance and data rate parameters are here proposed. The developed algorithms have been extensively simulated and the architectures were synthesized so that the results can serve as a reference for other works in the area