Medidor de massa magra para seres humanos

Seja por motivos de saúde, estéticos ou de desempenho físico, cada vez mais há interesse em conhecer o próprio percentual de gordura corporal (%GC). Métodos cada vez menos invasivos e menos intrusivos vem sendo pesquisados para obter tal medida com o mínimo de desconforto para o paciente. Infelizmente, equipamentos de medição do %GC que apresentem operação simples, baixo custo e que possibilitem que o próprio paciente realize a medição não são encontrados no mercado nacional. O objetivo maior deste trabalho consiste, por isso, em propor um medidor com estas características. Para isso, verifica-se a possibilidade de utilizar um método com ultra-som de baixa freqüência para obter as espessuras de tecido adiposo subcutâneo e a partir disto, o %GC. Devido à elevada sensibilidade ao posicionamento do corpo de prova verificada, o que ocasiona total falta de repetibilidade das medidas, o uso de tal método é descartado. Como alternativa, propõe-se o uso do método de bioimpedância para o medidor. Os detalhes de projeto de tal equipamento são discutidos e um protótipo de suas partes críticas é implementado para mostrar sua viabilidade. A análise do protótipo construído demonstra que o equipamento devidamente acabado, quando operado em modo de bioimpedância total, apresentará precisão, exatidão, facilidade de operação e custo adequados ao uso proposto. Na operação em modo de bioimpedância segmental, todavia, a exatidão das medidas obtidas deixa a desejar, devido à provável inadequação das equações de predição usadas.

Designing single event upset mitigation techniques for large SRAM-Based FPGA components

This thesis presents the study and development of fault-tolerant techniques for programmable architectures, the well-known Field Programmable Gate Arrays (FPGAs), customizable by SRAM. FPGAs are becoming more valuable for space applications because of the high density, high performance, reduced development cost and re-programmability. In particular, SRAM-based FPGAs are very valuable for remote missions because of the possibility of being reprogrammed by the user as many times as necessary in a very short period. SRAM-based FPGA and micro-controllers represent a wide range of components in space applications, and as a result will be the focus of this work, more specifically the Virtex® family from Xilinx and the architecture of the 8051 micro-controller from Intel. The Triple Modular Redundancy (TMR) with voters is a common high-level technique to protect ASICs against single event upset (SEU) and it can also be applied to FPGAs. The TMR technique was first tested in the Virtex® FPGA architecture by using a small design based on counters. Faults were injected in all sensitive parts of the FPGA and a detailed analysis of the effect of a fault in a TMR design synthesized in the Virtex® platform was performed. Results from fault injection and from a radiation ground test facility showed the efficiency of the TMR for the related case study circuit. Although TMR has showed a high reliability, this technique presents some limitations, such as area overhead, three times more input and output pins and, consequently, a significant increase in power dissipation. Aiming to reduce TMR costs and improve reliability, an innovative high-level technique for designing fault-tolerant systems in SRAM-based FPGAs was developed, without modification in the FPGA architecture. This technique combines time and hardware redundancy to reduce overhead and to ensure reliability. It is based on duplication with comparison and concurrent error detection. The new technique proposed in this work was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. The thesis presents comparison results in fault coverage, area and performance between the discussed techniques.