Functional timing analysis of VLSI circuits containing complex gates

The recent advances in CMOS technology have allowed for the fabrication of transistors with submicronic dimensions, making possible the integration of tens of millions devices in a single chip that can be used to build very complex electronic systems. Such increase in complexity of designs has originated a need for more efficient verification tools that could incorporate more appropriate physical and computational models. Timing verification targets at determining whether the timing constraints imposed to the design may be satisfied or not. It can be performed by using circuit simulation or by timing analysis. Although simulation tends to furnish the most accurate estimates, it presents the drawback of being stimuli dependent. Hence, in order to ensure that the critical situation is taken into account, one must exercise all possible input patterns. Obviously, this is not possible to accomplish due to the high complexity of current designs. To circumvent this problem, designers must rely on timing analysis. Timing analysis is an input-independent verification approach that models each combinational block of a circuit as a direct acyclic graph, which is used to estimate the critical delay. First timing analysis tools used only the circuit topology information to estimate circuit delay, thus being referred to as topological timing analyzers. However, such method may result in too pessimistic delay estimates, since the longest paths in the graph may not be able to propagate a transition, that is, may be false. Functional timing analysis, in turn, considers not only circuit topology, but also the temporal and functional relations between circuit elements. Functional timing analysis tools may differ by three aspects: the set of sensitization conditions necessary to declare a path as sensitizable (i.e., the so-called path sensitization criterion), the number of paths simultaneously handled and the method used to determine whether sensitization conditions are satisfiable or not. Currently, the two most efficient approaches test the sensitizability of entire sets of paths at a time: one is based on automatic test pattern generation (ATPG) techniques and the other translates the timing analysis problem into a satisfiability (SAT) problem. Although timing analysis has been exhaustively studied in the last fifteen years, some specific topics have not received the required attention yet. One such topic is the applicability of functional timing analysis to circuits containing complex gates. This is the basic concern of this thesis. In addition, and as a necessary step to settle the scenario, a detailed and systematic study on functional timing analysis is also presented.

Mixed-signal analog-digital circuits design on the pre-diffused digital array using trapezoidal association of transistors

The mixed-signal and analog design on a pre-diffused array is a challenging task, given that the digital array is a linear matrix arrangement of minimum-length transistors. To surmount this drawback a specific discipline for designing analog circuits over such array is required. An important novel technique proposed is the use of TAT (Trapezoidal Associations of Transistors) composite transistors on the semi-custom Sea-Of-Transistors (SOT) array. The analysis and advantages of TAT arrangement are extensively analyzed and demonstrated, with simulation and measurement comparisons to equivalent single transistors. Basic analog cells were also designed as well in full-custom and TAT versions in 1.0mm and 0.5mm digital CMOS technologies. Most of the circuits were prototyped in full-custom and TAT-based on pre-diffused SOT arrays. An innovative demonstration of the TAT technique is shown with the design and implementation of a mixed-signal analog system, i. e., a fully differential 2nd order Sigma-Delta Analog-to-Digital (A/D) modulator, fabricated in both full-custom and SOT array methodologies in 0.5mm CMOS technology from MOSIS foundry. Three test-chips were designed and fabricated in 0.5mm. Two of them are IC chips containing the full-custom and SOT array versions of a 2nd-Order Sigma-Delta A/D modulator. The third IC contains a transistors-structure (TAT and single) and analog cells placed side-by-side, block components (Comparator and Folded-cascode OTA) of the Sigma-Delta modulator.

Quantificação de Shunt intrapulmonar por cintilografia e gasometria arterial com 02 a 100% em candidatos a transplante hepático com diferentes graus de dilatação vascular intrapulmonar

As dilatações vasculares intrapulmonares (DVIP) constituem a anormalidade vascular pulmonar mais freqüente e a principal causa de hipoxemia grave em hepatopatas. A associação de doença hepática, aumento do gradiente alvéoloarterial de oxigênio e DVIP é chamada de "síndrome hepatopulmonar". O objetivo principal deste estudo foi verificar se os níveis de DVIP aferidos por ecocardiografia com contraste estão relacionados à intensidade de shunt intrapulmonar, medida por dois diferentes métodos: cintilografia com 99mTc-MAA e gasometria com O2 a 100%. Foram estudados 28 candidatos a transplante hepático portadores com DVIP identificadas e graduadas por ecocardiografia conforme escala semi-quantitativa (graus I a IV). A idade média foi de 47,5 anos, e a doença hepática foi classificada como Child-Pugh B na maioria dos casos (60,7%). A intensidade das DVIP foi classificada como I, II, III e IV em 13 (46,4%), 9 (32,1%), 2 (7,1%) e 4 (14,3%) casos, respectivamente. Dos 28 pacientes, 21 (75%) tiveram quantificação de shunt pelo método cintigráfico e gasométrico, 6 (21,4%) apenas pelo método cintigráfico e 1 caso (3,6%) pelo método gasométrico apenas. A PaO2 média entre os pacientes com DVIP graus I e II por ecocardiografia foi 89,1 ± 11,0mmHg, enquanto naqueles com DVIP classificadas como graus III e IV foi 74,7 ± 13,2mmHg (p = 0,01). A média dos valores de shunt por cintilografia nos 27 pacientes submetidos ao exame foi 14,9 ± 9,0% do débito cardíaco (mínimo 6,9% e máximo 39%), sendo 11,7 ± 3,8% nos pacientes com DVIP graus I e II, e 26,3 ± 9,7% nos pacientes com DVIP graus III e IV (p = 0,01). A média dos valores de shunt pelo teste com O2a 100% foi 9,8 ± 3,9%, sendo 8,3 ± 2,3% nos pacientes com DVIP graus I e II, e 16,3 ± 2,6% nos pacientes com DVIP graus III e IV (p < 0,001). Observou-se uma relação estatisticamente significativa entre a graduação de DVIP por ecocardiografia e o valor de shunt aferido por gasometria com O2 a 100% (rs = 0,609, p < 0,01) e por cintilografia (rs = 0,567, p < 0,001). Observou-se relação estatisticamente significativa entre os valores de shunt medidos por cintilografia e aqueles medidos por gasometria com O2 a 100% nos 21 pacientes que se submeteram à quantificação de shunt pelos 2 métodos (rs = 0,666, p < 0,001). A avaliação semi-quantitativa do grau de DVIP por ecocardiografia apresentou correlação moderada a boa com os valores de shunt aferidos pelos dois outros métodos estudados, sendo que a melhor correlação foi observada com o teste com O2 a 100%.

Automatic layout generation of static CMOS circuits targeting delay and power

The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.

Low cost BIST techniques for linear and non-linear analog circuits

With the ever increasing demands for high complexity consumer electronic products, market pressures demand faster product development and lower cost. SoCbased design can provide the required design flexibility and speed by allowing the use of IP cores. However, testing costs in the SoC environment can reach a substantial percent of the total production cost. Analog testing costs may dominate the total test cost, as testing of analog circuits usually require functional verification of the circuit and special testing procedures. For RF analog circuits commonly used in wireless applications, testing is further complicated because of the high frequencies involved. In summary, reducing analog test cost is of major importance in the electronic industry today. BIST techniques for analog circuits, though potentially able to solve the analog test cost problem, have some limitations. Some techniques are circuit dependent, requiring reconfiguration of the circuit being tested, and are generally not usable in RF circuits. In the SoC environment, as processing and memory resources are available, they could be used in the test. However, the overhead for adding additional AD and DA converters may be too costly for most systems, and analog routing of signals may not be feasible and may introduce signal distortion. In this work a simple and low cost digitizer is used instead of an ADC in order to enable analog testing strategies to be implemented in a SoC environment. Thanks to the low analog area overhead of the converter, multiple analog test points can be observed and specific analog test strategies can be enabled. As the digitizer is always connected to the analog test point, it is not necessary to include muxes and switches that would degrade the signal path. For RF analog circuits, this is specially useful, as the circuit impedance is fixed and the influence of the digitizer can be accounted for in the design phase. Thanks to the simplicity of the converter, it is able to reach higher frequencies, and enables the implementation of low cost RF test strategies. The digitizer has been applied successfully in the testing of both low frequency and RF analog circuits. Also, as testing is based on frequency-domain characteristics, nonlinear characteristics like intermodulation products can also be evaluated. Specifically, practical results were obtained for prototyped base band filters and a 100MHz mixer. The application of the converter for noise figure evaluation was also addressed, and experimental results for low frequency amplifiers using conventional opamps were obtained. The proposed method is able to enhance the testability of current mixed-signal designs, being suitable for the SoC environment used in many industrial products nowadays.