Functional timing analysis of VLSI circuits containing complex gates

The recent advances in CMOS technology have allowed for the fabrication of transistors with submicronic dimensions, making possible the integration of tens of millions devices in a single chip that can be used to build very complex electronic systems. Such increase in complexity of designs has originated a need for more efficient verification tools that could incorporate more appropriate physical and computational models. Timing verification targets at determining whether the timing constraints imposed to the design may be satisfied or not. It can be performed by using circuit simulation or by timing analysis. Although simulation tends to furnish the most accurate estimates, it presents the drawback of being stimuli dependent. Hence, in order to ensure that the critical situation is taken into account, one must exercise all possible input patterns. Obviously, this is not possible to accomplish due to the high complexity of current designs. To circumvent this problem, designers must rely on timing analysis. Timing analysis is an input-independent verification approach that models each combinational block of a circuit as a direct acyclic graph, which is used to estimate the critical delay. First timing analysis tools used only the circuit topology information to estimate circuit delay, thus being referred to as topological timing analyzers. However, such method may result in too pessimistic delay estimates, since the longest paths in the graph may not be able to propagate a transition, that is, may be false. Functional timing analysis, in turn, considers not only circuit topology, but also the temporal and functional relations between circuit elements. Functional timing analysis tools may differ by three aspects: the set of sensitization conditions necessary to declare a path as sensitizable (i.e., the so-called path sensitization criterion), the number of paths simultaneously handled and the method used to determine whether sensitization conditions are satisfiable or not. Currently, the two most efficient approaches test the sensitizability of entire sets of paths at a time: one is based on automatic test pattern generation (ATPG) techniques and the other translates the timing analysis problem into a satisfiability (SAT) problem. Although timing analysis has been exhaustively studied in the last fifteen years, some specific topics have not received the required attention yet. One such topic is the applicability of functional timing analysis to circuits containing complex gates. This is the basic concern of this thesis. In addition, and as a necessary step to settle the scenario, a detailed and systematic study on functional timing analysis is also presented.

Efeitos da variação da carga por eixo, pressão de inflação e tipo de pneu na resposta elástica de um pavimento

O presente trabalho é uma análise experimental que procura investigar os efeitos dos fatores carga por eixo, pressão de inflação e tipo de pneu sobre o desempenho de pavimentos. Os dados e informações existentes sobre o quadro de cargas por eixo praticada pela frota de veículos pesados é razoável. A ação conjunta dos referidos fatores é ainda uma questão pouco explorada. Assim, para compensar a escassez de dados sobre pressão de inflação e tipo de construção de pneus utilizados na frota de carga, programou-se uma pesquisa de campo na rodovia estadual RS/240. As informações oriundas da pesquisa demonstram que há um acréscimo generalizado no valor da pressão dos pneus e um aumento de uso dos pneus de fabricação radial em relação aos pneus convencionais. Os dados de campo subsidiaram a programação de um experimento fatorial cruzado executado na Área de Pesquisas e Testes de Pavimentos da UFRGS/DAER. A variação dos níveis dos fatores deu-se através de um simulador linear de tráfego atuando sobre uma pista experimental com 20 m de comprimento por 3,5 m de largura. Tendo como resposta estrutural do pavimento a máxima deflexão superficial recuperável medida com uma viga Benkelmam, determinou-se como significantes os efeitos dos fatores carga por eixo e pressão de enchimento dos pneus. Os cálculos estatísticos indicam também que não há diferenças significativas entre os pneus tipo 9.00R20 e 9.00x20 e que todas interações não exercem efeitos significativos sobre a variável de resposta. Em seqüência, determinaram-se as áreas de contato do rodado duplo do simulador de tráfego com a superfície do pavimento ensaiado para as combinações dos níveis dos fatores. Pode-se, então, comparar área de contato medida com área circular calculada, considerada em muitos modelos de dimensionamento de pavimentos. Relacionou-se a variação da pressão de contato com a deflexão recuperável e procedeu-se uma comparação da mesma com a pressão de inflação nominal dos pneus. Apresenta-se um modelo de análise do desempenho do pavimento em função da carga por eixo e da pressão de inflação, nos limites do experimento. Os dados decorrentes do experimento viabilizaram a determinação dos Fatores de Equivalência de Cargas para os níveis dos fatores, considerando-se o pavimento ensaiado. Avaliou-se, via evolução das deflexões e dos Fatores de Equivalência de Cargas, a redução da vida do pavimento, obtendo-se, para a combinação de níveis mais críticos de carregamento, resultados significativos de até 88 % de redução. Propõe-se, por último, uma formulação para o Fator de Equivalência de Cargas que considere também a ação da pressão de inflação.

Reuse-based test planning for core-based systems-on-chip

Electronic applications are currently developed under the reuse-based paradigm. This design methodology presents several advantages for the reduction of the design complexity, but brings new challenges for the test of the final circuit. The access to embedded cores, the integration of several test methods, and the optimization of the several cost factors are just a few of the several problems that need to be tackled during test planning. Within this context, this thesis proposes two test planning approaches that aim at reducing the test costs of a core-based system by means of hardware reuse and integration of the test planning into the design flow. The first approach considers systems whose cores are connected directly or through a functional bus. The test planning method consists of a comprehensive model that includes the definition of a multi-mode access mechanism inside the chip and a search algorithm for the exploration of the design space. The access mechanism model considers the reuse of functional connections as well as partial test buses, cores transparency, and other bypass modes. The test schedule is defined in conjunction with the access mechanism so that good trade-offs among the costs of pins, area, and test time can be sought. Furthermore, system power constraints are also considered. This expansion of concerns makes it possible an efficient, yet fine-grained search, in the huge design space of a reuse-based environment. Experimental results clearly show the variety of trade-offs that can be explored using the proposed model, and its effectiveness on optimizing the system test plan. Networks-on-chip are likely to become the main communication platform of systemson- chip. Thus, the second approach presented in this work proposes the reuse of the on-chip network for the test of the cores embedded into the systems that use this communication platform. A power-aware test scheduling algorithm aiming at exploiting the network characteristics to minimize the system test time is presented. The reuse strategy is evaluated considering a number of system configurations, such as different positions of the cores in the network, power consumption constraints and number of interfaces with the tester. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized. In this manuscript, the main problems of the test of core-based systems are firstly identified and the current solutions are discussed. The problems being tackled by this thesis are then listed and the test planning approaches are detailed. Both test planning techniques are validated for the recently released ITC’02 SoC Test Benchmarks, and further compared to other test planning methods of the literature. This comparison confirms the efficiency of the proposed methods.