Projetos de controladores para sistemas de potência utilizando LMI'S

A presente dissertação tem como objetivo estudar e aprimorar métodos de projetos de controladores para sistemas de potência, sendo que esse trabalho trata da estabilidade dinâmica de sistemas de potência e, portanto, do projeto de controladores amortecedores de oscilações eletromecânicas para esses sistemas. A escolha dos métodos aqui estudados foi orientada pelos requisitos que um estabilizador de sistemas de potência (ESP) deve ter, que são robustez, descentralização e coordenação. Sendo que alguns deles tiveram suas características aprimoradas para atender a esses requisitos. A abordagem dos métodos estudados foi restringida à análise no domínio tempo, pois a abordagem temporal facilita a modelagem das incertezas paramétricas, para atender ao requisito da robustez, e também permite a formulação do controle descentralizado de maneira simples. Além disso, a abordagem temporal permite a formulação do problema de projeto utilizando desigualdades matriciais lineares (LMI’s), as quais possuem como vantagem o fato do conjunto solução ser sempre convexo e a existência de algoritmos eficientes para o cálculo de sua solução. De fato, existem diversos pacotes computacionais desenvolvidos no mercado para o cálculo da solução de um problema de inequações matriciais lineares. Por esse motivo, os métodos de projeto para controladores de saída buscam sempre colocar o problema na forma de LMI’s, tendo em vista que ela garante a obtenção de solução, caso essa solução exista.

Reuse-based test planning for core-based systems-on-chip

Electronic applications are currently developed under the reuse-based paradigm. This design methodology presents several advantages for the reduction of the design complexity, but brings new challenges for the test of the final circuit. The access to embedded cores, the integration of several test methods, and the optimization of the several cost factors are just a few of the several problems that need to be tackled during test planning. Within this context, this thesis proposes two test planning approaches that aim at reducing the test costs of a core-based system by means of hardware reuse and integration of the test planning into the design flow. The first approach considers systems whose cores are connected directly or through a functional bus. The test planning method consists of a comprehensive model that includes the definition of a multi-mode access mechanism inside the chip and a search algorithm for the exploration of the design space. The access mechanism model considers the reuse of functional connections as well as partial test buses, cores transparency, and other bypass modes. The test schedule is defined in conjunction with the access mechanism so that good trade-offs among the costs of pins, area, and test time can be sought. Furthermore, system power constraints are also considered. This expansion of concerns makes it possible an efficient, yet fine-grained search, in the huge design space of a reuse-based environment. Experimental results clearly show the variety of trade-offs that can be explored using the proposed model, and its effectiveness on optimizing the system test plan. Networks-on-chip are likely to become the main communication platform of systemson- chip. Thus, the second approach presented in this work proposes the reuse of the on-chip network for the test of the cores embedded into the systems that use this communication platform. A power-aware test scheduling algorithm aiming at exploiting the network characteristics to minimize the system test time is presented. The reuse strategy is evaluated considering a number of system configurations, such as different positions of the cores in the network, power consumption constraints and number of interfaces with the tester. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized. In this manuscript, the main problems of the test of core-based systems are firstly identified and the current solutions are discussed. The problems being tackled by this thesis are then listed and the test planning approaches are detailed. Both test planning techniques are validated for the recently released ITC’02 SoC Test Benchmarks, and further compared to other test planning methods of the literature. This comparison confirms the efficiency of the proposed methods.