Designing single event upset mitigation techniques for large SRAM-Based FPGA components

This thesis presents the study and development of fault-tolerant techniques for programmable architectures, the well-known Field Programmable Gate Arrays (FPGAs), customizable by SRAM. FPGAs are becoming more valuable for space applications because of the high density, high performance, reduced development cost and re-programmability. In particular, SRAM-based FPGAs are very valuable for remote missions because of the possibility of being reprogrammed by the user as many times as necessary in a very short period. SRAM-based FPGA and micro-controllers represent a wide range of components in space applications, and as a result will be the focus of this work, more specifically the Virtex® family from Xilinx and the architecture of the 8051 micro-controller from Intel. The Triple Modular Redundancy (TMR) with voters is a common high-level technique to protect ASICs against single event upset (SEU) and it can also be applied to FPGAs. The TMR technique was first tested in the Virtex® FPGA architecture by using a small design based on counters. Faults were injected in all sensitive parts of the FPGA and a detailed analysis of the effect of a fault in a TMR design synthesized in the Virtex® platform was performed. Results from fault injection and from a radiation ground test facility showed the efficiency of the TMR for the related case study circuit. Although TMR has showed a high reliability, this technique presents some limitations, such as area overhead, three times more input and output pins and, consequently, a significant increase in power dissipation. Aiming to reduce TMR costs and improve reliability, an innovative high-level technique for designing fault-tolerant systems in SRAM-based FPGAs was developed, without modification in the FPGA architecture. This technique combines time and hardware redundancy to reduce overhead and to ensure reliability. It is based on duplication with comparison and concurrent error detection. The new technique proposed in this work was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. The thesis presents comparison results in fault coverage, area and performance between the discussed techniques.

Projetos de controladores para sistemas de potência utilizando LMI'S

A presente dissertação tem como objetivo estudar e aprimorar métodos de projetos de controladores para sistemas de potência, sendo que esse trabalho trata da estabilidade dinâmica de sistemas de potência e, portanto, do projeto de controladores amortecedores de oscilações eletromecânicas para esses sistemas. A escolha dos métodos aqui estudados foi orientada pelos requisitos que um estabilizador de sistemas de potência (ESP) deve ter, que são robustez, descentralização e coordenação. Sendo que alguns deles tiveram suas características aprimoradas para atender a esses requisitos. A abordagem dos métodos estudados foi restringida à análise no domínio tempo, pois a abordagem temporal facilita a modelagem das incertezas paramétricas, para atender ao requisito da robustez, e também permite a formulação do controle descentralizado de maneira simples. Além disso, a abordagem temporal permite a formulação do problema de projeto utilizando desigualdades matriciais lineares (LMI’s), as quais possuem como vantagem o fato do conjunto solução ser sempre convexo e a existência de algoritmos eficientes para o cálculo de sua solução. De fato, existem diversos pacotes computacionais desenvolvidos no mercado para o cálculo da solução de um problema de inequações matriciais lineares. Por esse motivo, os métodos de projeto para controladores de saída buscam sempre colocar o problema na forma de LMI’s, tendo em vista que ela garante a obtenção de solução, caso essa solução exista.