Formulação LTSn para problemas de transporte sem simetria azimutal e problemas dependentes do tempo

Neste trabalho, estendemos, de forma analítica, a formulação LTSN à problemas de transporte unidimensionais sem simetria azimutal. Para este problema, também apresentamos a solução com dependência contínua na variável angular, a partir da qual é estabelecido um método iterativo de solução da equação de transporte unidimensional. Também discutimos como a formulação LTSN é aplicada na resolução de problemas de transporte unidimensionais dependentes do tempo, tanto de forma aproximada pela inversão numérica do fluxo transformado na variável tempo, bem como analiticamente, pela aplicação do método LTSNnas equações nodais. Simulações numéricas e comparações com resultados disponíveis na literatura são apresentadas.

Mixed-signal analog-digital circuits design on the pre-diffused digital array using trapezoidal association of transistors

The mixed-signal and analog design on a pre-diffused array is a challenging task, given that the digital array is a linear matrix arrangement of minimum-length transistors. To surmount this drawback a specific discipline for designing analog circuits over such array is required. An important novel technique proposed is the use of TAT (Trapezoidal Associations of Transistors) composite transistors on the semi-custom Sea-Of-Transistors (SOT) array. The analysis and advantages of TAT arrangement are extensively analyzed and demonstrated, with simulation and measurement comparisons to equivalent single transistors. Basic analog cells were also designed as well in full-custom and TAT versions in 1.0mm and 0.5mm digital CMOS technologies. Most of the circuits were prototyped in full-custom and TAT-based on pre-diffused SOT arrays. An innovative demonstration of the TAT technique is shown with the design and implementation of a mixed-signal analog system, i. e., a fully differential 2nd order Sigma-Delta Analog-to-Digital (A/D) modulator, fabricated in both full-custom and SOT array methodologies in 0.5mm CMOS technology from MOSIS foundry. Three test-chips were designed and fabricated in 0.5mm. Two of them are IC chips containing the full-custom and SOT array versions of a 2nd-Order Sigma-Delta A/D modulator. The third IC contains a transistors-structure (TAT and single) and analog cells placed side-by-side, block components (Comparator and Folded-cascode OTA) of the Sigma-Delta modulator.