Designing single event upset mitigation techniques for large SRAM-Based FPGA components

This thesis presents the study and development of fault-tolerant techniques for programmable architectures, the well-known Field Programmable Gate Arrays (FPGAs), customizable by SRAM. FPGAs are becoming more valuable for space applications because of the high density, high performance, reduced development cost and re-programmability. In particular, SRAM-based FPGAs are very valuable for remote missions because of the possibility of being reprogrammed by the user as many times as necessary in a very short period. SRAM-based FPGA and micro-controllers represent a wide range of components in space applications, and as a result will be the focus of this work, more specifically the Virtex® family from Xilinx and the architecture of the 8051 micro-controller from Intel. The Triple Modular Redundancy (TMR) with voters is a common high-level technique to protect ASICs against single event upset (SEU) and it can also be applied to FPGAs. The TMR technique was first tested in the Virtex® FPGA architecture by using a small design based on counters. Faults were injected in all sensitive parts of the FPGA and a detailed analysis of the effect of a fault in a TMR design synthesized in the Virtex® platform was performed. Results from fault injection and from a radiation ground test facility showed the efficiency of the TMR for the related case study circuit. Although TMR has showed a high reliability, this technique presents some limitations, such as area overhead, three times more input and output pins and, consequently, a significant increase in power dissipation. Aiming to reduce TMR costs and improve reliability, an innovative high-level technique for designing fault-tolerant systems in SRAM-based FPGAs was developed, without modification in the FPGA architecture. This technique combines time and hardware redundancy to reduce overhead and to ensure reliability. It is based on duplication with comparison and concurrent error detection. The new technique proposed in this work was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. The thesis presents comparison results in fault coverage, area and performance between the discussed techniques.

Desenvolvimento de elastômeros termoplásticos a partir de SBR epoxidada e polipropileno

Os elastômeros termoplásticos vulcanizados (TPVs) na sua maioria constituídos por borrachas apolares (EPDM, NR) e poliolefinas (PP, PE), apresentam a vantagem de serem processáveis como termoplásticos e serem facilmente reciclados. No entanto, apresentam desvantagens no que se refere à sua baixa resistência a óleos, combustíveis e graxas em relação à borracha termofixa. Este trabalho, teve como objetivo estudar a obtenção de TPVs com propriedades mecânicas adequadas e resistência a óleos e solventes orgânicos, a partir da borracha comercial SBR 1502 parcialmente epoxidada. Esta, por ter a estrutura química de sua cadeia principal modificada pela introdução de grupos epóxidos, deve apresentar melhor resistência a óleos e solventes. Os TPVs foram obtidos em misturador fechado acoplado a um reômetro Haake, na temperatura de 1800C e velocidade de rotor de 75 rpm, vulcanizados dinamicamente com o sistema Bismaleimida/peróxido de dicumila. Foram caracterizados quanto às suas propriedades mecânicas por medidas tensão-deformação, medidas mecânicas dinâmicas, inchamento em ciclohexano, THF e óleo IRM 903, dureza. A morfologia foi determinada por microscopia eletrônica de varredura, MEV. Foram analisados os fatores que influenciam as propriedades dos TPVs, tais como composição (relação PP/SBR), teor de BMI, grau de epoxidação da borracha, uso de agente compatibilizante. O TPV na composição PP/SBR 40/60, esta epoxidada em 40 mol % e contendo o agente compatibilizante Vestenamer adicionado na forma de blenda (borracha/agente compatibilizante) apresentou a melhor resposta em termos de tensão-deformação na ruptura. Os TPVs com a SBR epoxidada em 70% apresentaram melhor resistência a óleo e solventes. Os fatores, potencialmente, capazes de influenciar a dureza dos TPVs também foram avaliados. Neste particular, verificou-se que o tipo de poliolefina, bem como o uso de plastificante são os fatores que mais influenciam a dureza dos TPVs.