The politics of memory in Harold Pinter's Ashes to Ashes

The present work proposes an investigation of the treatment given to memory in Pinter’s latest play, Ashes to Ashes, and of its function in the development of Pinter’s work. In order to do that, different aspects of the construction of meaning in the theatre are analysed, so that the specificity of its reception is determined. A survey of techniques used to present information, time and space in the theatre is made. The analytical drama, the history drama, and the theatre of the absurd are defined. After that, the evolution of the author’s work is analysed to determine what characterises Pinter’s work, while at the same time determining how his treatment of themes like menace, memory, and political oppression of the individual has evolved. Finally, a detailed survey of the apparently disconnected elements that are mentioned in Ashes to Ashes is made. The intertextual analysis allied to a study of the analytical form as used in this play enables the discovery of several layers of meaning. Through the connection established between the Holocaust and man’s fall followed by expulsion from Eden, Pinter examines the use of memory as a way of dealing with personal and collective responsibility and guilt. It is through the recovery of memory (also through writing) that the present can establish a critical and responsible relation with the past.

Designing single event upset mitigation techniques for large SRAM-Based FPGA components

This thesis presents the study and development of fault-tolerant techniques for programmable architectures, the well-known Field Programmable Gate Arrays (FPGAs), customizable by SRAM. FPGAs are becoming more valuable for space applications because of the high density, high performance, reduced development cost and re-programmability. In particular, SRAM-based FPGAs are very valuable for remote missions because of the possibility of being reprogrammed by the user as many times as necessary in a very short period. SRAM-based FPGA and micro-controllers represent a wide range of components in space applications, and as a result will be the focus of this work, more specifically the Virtex® family from Xilinx and the architecture of the 8051 micro-controller from Intel. The Triple Modular Redundancy (TMR) with voters is a common high-level technique to protect ASICs against single event upset (SEU) and it can also be applied to FPGAs. The TMR technique was first tested in the Virtex® FPGA architecture by using a small design based on counters. Faults were injected in all sensitive parts of the FPGA and a detailed analysis of the effect of a fault in a TMR design synthesized in the Virtex® platform was performed. Results from fault injection and from a radiation ground test facility showed the efficiency of the TMR for the related case study circuit. Although TMR has showed a high reliability, this technique presents some limitations, such as area overhead, three times more input and output pins and, consequently, a significant increase in power dissipation. Aiming to reduce TMR costs and improve reliability, an innovative high-level technique for designing fault-tolerant systems in SRAM-based FPGAs was developed, without modification in the FPGA architecture. This technique combines time and hardware redundancy to reduce overhead and to ensure reliability. It is based on duplication with comparison and concurrent error detection. The new technique proposed in this work was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. The thesis presents comparison results in fault coverage, area and performance between the discussed techniques.