Macroergonomia em Call Center de ambiente universitário

Este estudo trata da abordagem macroergonômica participativa para a identificação das demandas ergonômicas dos atendentes que operam em central de atendimento universitária, com utilização da metodologia participativa da Análise Macroergonômica do Trabalho (AMT) (Guimarães, 2001) e feITaIllentalproposto no DesignMacroergonômico (DM) (Fogliatto e Guimarães, 1999). o estudo de caso foi realizado em uma Instituição Federal de Ensino - IFE. A aplicação da metodologia permitiu identificar demandas prioritárias através das fases de apreciação e diagnóstico que possibilitaram a formulação de recomendações e diretrizes para introdução de meJhorias a serem estudadas e detalhadas nas demais fases do método. Os estudos realizados também permitem identificar uma especial afinidade da metodologia participativa com uma instituição pública democrática, em que as mudanças podem ocorrer de foma gradativa, em função dos escassos recursos disponíveis, vislumbrando-se o atendimento, por ordem de importância, dos itens de demanda ergonômica. Por fim, estabeleceu-se uma proposta inicial de um modelo de implementação da metodologia no âmbito da instituição, através da integração multidisciplinar e multidepartamental dos profissionais das áreas técnicas e de saúde e dos representantes dos docentes, técnicos-administrativos e discentes, utilizando-se a estruturajá existente e, por conseqüência, sem custos adicionais.

Automatic layout generation of static CMOS circuits targeting delay and power

The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.