Analysis of multi-cluster computing systems with processor heterogeneity

This paper addresses the problem of performance modeling of heterogeneous multi-cluster computing systems. We present an analytical model that can be employed to explore the effectiveness of different design approaches so that one can have an intelligent choice during design and evaluation of a cost effective large-scale heterogeneous distributed computing system. The proposed model considers stochastic quantities as well as processor heterogeneity of the target system. The analysis is based on a parametric fat-tree network, the m-port n-tree, and a deterministic routing algorithm. The correctness of the proposed model is validated through comprehensive simulation of different types of clusters.

Structured development of an asynchronous forth processor using trace theory

This thesis examines the use of a structured design methodology in the design of asynchronous circuits so that high level constructs can be specified purely in terms of signal exchanges and without the intrusion of lower level concepts. Trace theory is used to specify a multi-processor Forth machine at a high level then part of the design is further elaborated using trace theory operations to (insure that the behaviours of the lower level constructs will combine to give the high level specified behaviour without locking or other hazards. A novel form of threaded language to take advantage of the machine architecture is developed. At suitable points the design is tested by simulation. The stack element which is designed is reduced to an electric circuit which is itself tested by simulation to verify the design.

A profiling based task scheduling approach for multicore network processors

 Multicore network processors have been playing an increasingly important role in computational processes, which emphasize on scalability and parallelism of the systems, in distributed environments especially in Internet-based delay-sensitive applications. It is an important but unsolved issue, however, to efficiently schedule tasks in network processors with multicore and multithread for improving the system throughput as much as possible. Profiling can gather runtime environment information and guide the compiler to optimize programs through scheduling tasks based on the runtime context. This paper proposes a profiling-based task scheduling approach, targeting on improving the throughput of multicore network processor (Intel IXP) systems in the balanced pipeline way. In this work, we investigate a profiling-based task scheduling framework, a task scheduling algorithm, and a set of performance models. Our task allocation scheme maps tasks onto the pipeline architecture and multiple threads of network processors in parallel, which incorporates the profiling context and global thread refinement. We evaluate our task scheduling algorithm by implementing representative network applications on the Intel IXP network processor. Experimental results demonstrate that our algorithm is able to schedule tasks in a balanced pipeline fashion and achieve the high throughput and data transmission rate. Copyright © 2012 John Wiley & Sons, Ltd.

Implementation of soft processor based SOC for JPEG compression on FPGA

With the advent of semiconductor process and EDA tools technology, IC designers can integrate more functions. However, to reduce the demand of time-to-market and tackle the increasing complexity of SoC, the need of fast prototyping and testing is growing. Taking advantage of deep submicron technology, modern FPGAs provide a fast and low-cost prototyping with large logic resources and high performance. So the hardware is mapped onto an emulation platform based on FPGA that mimics the behaviour of SOC. In this paper we use FPGA as a system on chip which is then used for image compression by 2-D DCT respectively and proposed SoC for image compression using soft core Microblaze. The JPEG standard defines compression techniques for image data. As a consequence, it allows to store and transfer image data with considerably reduced demand for storage space and bandwidth. From the four processes provided in the JPEG standard, only one, the baseline process is widely used. Proposed SoC for JPEG compression has been implemented on FPGA Spartan-6 SP605 evaluation board using Xilinx platform studio, because field programmable gate array have reconfigurable hardware architecture. Hence the JPEG image with high speed and reduced size can be obtained at low risk and low power consumption of about 0.699W. The proposed SoC for image compression is evaluated at 83.33MHz on Xilinx Spartan-6 FPGA.

A digital signal processor controlled smart battery charger for photovoltaic power systems

An off-grid photovoltaic power system requires an energy storage system, especially batteries, for mitigation of variability and intermittency problems, and for assured service reliability and availability. The longevity and reliability of such batteries depend on the effectiveness of the charging system. This paper presents the modelling, simulation and hardware implementation of a four-stage switch-mode charger based on the single-ended primary inductance converter. The digital signal processor based controller implements algorithms for the system's power balance control, maximum power point tracking to improve charging speed and efficiency, four-stage optimal charging, and system's protection. The protection algorithm provides over-charge, overdischarge, over-temperature and short circuit protection capabilities. The proposed system has the following advantages: ability to continuously charge the batteries even at reduced solar irradiation, higher efficiency, and use of adaptive thermally compensated set points for optimum performance. A prototype is built and experimental results are presented to validate the simulation results.

Fast algorithm for the cutting angle method of global optimization

The cutting angle method for global optimization was proposed in 1999 by Andramonov et al. (Appl. Math. Lett. 12 (1999) 95). Computer implementation of the resulting algorithm indicates that running time could be improved with appropriate modifications to the underlying mathematical description. In this article, we describe the initial algorithm and introduce a new one which we prove is significantly faster at each stage. Results of numerical experiments performed on a Pentium III 750 Mhz processor are presented.

Food industry awareness of consumers` plant food beliefs

Abstract: Purpose – The aims of this study were to examine farmers' and food processors' alignment with consumers' views about plant foods and their intentions to produce plant foods. Design/methodology/approach – Data on plant food beliefs were collected from mail surveys of farmers, food processing businesses and random population samples of adults in Victoria, Australia. Findings – There were strong differences between consumers' beliefs and farmers' and food processors' perceptions of consumers' beliefs. For example, a higher proportion of farmers and processors believed that consumers would eat more plant foods if more convenience-oriented plant-based meals were available than consumers themselves agreed. Farmers appeared to be more aware of or aligned with consumers' beliefs than were processors. One- and two-thirds of farmers and processors respectively were planning to grow or process more plant foods, which bodes well for the availability of plant and plant-based foods. Research limitations/implications – Study limitations include the small food industry sample sizes and possible response bias, although analysis suggests the latter was low. Future research could survey a larger sample of food industry representatives, including those from other sectors (e.g. retailers). Practical implications – Education of consumers and industry groups on plant foods and better lines of communication from consumer to processor to farmer, are required. Originality/value – To the authors' knowledge, this is the first study to examine farmers' and food processors' awareness of consumers' beliefs about plant foods. This issue is important for those involved with the production and marketing of plant foods or with food, farming and health policy.

Gang scheduling with a queue for large jobs

Applying gang scheduling can alleviate the blockade problem caused by exclusively space-sharing scheduling. To simply allow jobs to run simultaneously on the same processors as in conventional gang scheduling, however, may introduce a large number of time slots in the system. In consequence the cost of context switches will be greatly increased, and each running job can only obtain a small portion of resources including memory space and processor utilisation and so no jobs can finish their computations quickly. Therefore, the number of jobs allowed to run in the system should be limited. In this paper we present some experimental results to show that by limiting real large jobs time-sharing the same processors and applying the backfilling technique we can greatly reduce the average number of time slots in the system and significantly improve the performance of both small and large jobs.

On the development of an efficient coscheduling system

Applying gang scheduling can alleviate the blockade problem caused by exclusively space-sharing scheduling. To simply allow jobs to run simultaneously on the same processors as in the conventional gang scheduling, however, may introduce a large number of time slots in the system. In consequence the cost of context switches will be greatly increased, and each running job can only obtain a small portion of resources including memory space and processor utilisation and so no jobs can finish their computations quickly. In this paper we present some experimental results to show that to properly divide jobs into different classes and to apply different scheduling strategies to jobs of different classes can greatly reduce the average number of time slots in the system and significantly improve the performance in terms of average slowdown.

Parallel I/O scheduling in the presence of data duplication on multiprogrammed cluster computing systems

The widespread adoption of cluster computing as a high performance computing platform has seen the growth of data intensive scientific, engineering and commercial applications such as digital libraries, climate modeling, computational chemistry, computational fluid dynamics and image repositories. However, I/O subsystem performance has not been keeping pace with processor and memory performance, and is fast becoming the dominant factor in overall system performance.  Thus, parallel I/O has become a necessity in the face of performance improvements in other areas of computing systems. This paper addresses the problem of parallel I/O scheduling on cluster computing systems in the presence of data replication.  We propose two new I/O scheduling algorithms and evaluate the relative performance of the proposed policies against two existing approaches.  Simulation results show that the proposed policies perform substantially better than the baseline policies.

Data collection for global scheduling in the GENESIS system

In order to schedule parallel processes on available computers there is a need to collect information about different cluster resources. Currently, global scheduling of parallel processes of applications takes into consideration mainly processor load and only in a small number of projects memory utilization. Communication costs, which are high in clusters, are practically neglected. The aim of this paper is to report on our study into cluster parameter measurements, in particular those, which characterize communication costs, the development of the resource discovery server and its initial testing through the study of the influence of communication costs on parallel application performance.

Analytical communication networks model for enterprise grid computing

This paper addresses the problem of performance analysis based on the communication modeling of large-scale heterogeneous distributed systems, with an emphasis on enterprise Grid computing systems. The study of communication layers is important, as the overall performance of a distributed system often critically hinges on the effectiveness of this part. We propose an analytical model that is based on probabilistic analysis and queuing networks. The proposed model considers the processor as well as network heterogeneity of the enterprise Grid system. The model is validated through comprehensive simulations, which demonstrate that the proposed model exhibits a good degree of accuracy for various system sizes, and under different working conditions.

Communication network analysis of the enterprise grid systems

This paper addresses the problem of performance analysis based on communication modelling of largescale heterogeneous distributed systems with emphases on enterprise grid computing systems. The study of communication layers is important because the overall performance of a distributed system is often critically hinged on the effectiveness of this part. This model considers processor as well as network heterogeneity of target system. The model is validated through comprehensive simulation, which demonstrates that the proposed model exhibits a good degree of accuracy for various system sizes and under different working conditions. The proposed model is then used to investigate the performance analysis of typical systems.

Analytical interconnection networks model for multi-cluster computing systems

This paper addresses the problem of interconnection networks performance modeling of large-scale distributed systems with emphases on multi-cluster computing systems. The study of interconnection networks is important because the overall performance of a distributed system is often critically hinged on the effectiveness of its interconnection network. We present an analytical model that considers stochastic quantities as well as processor heterogeneity of the target system. The model is validated through comprehensive simulation, which demonstrates that the proposed model exhibits a good degree of accuracy for various system sizes and under different operating conditions.

Analytical modeling of communication latency in multi-cluster systems

This paper addresses the problem of performance modeling of large-scale distributed systems with emphasis on communication networks in heterogeneous multi-cluster systems. The study of interconnection networks is important because the overall performance of a distributed system is often critically hinged on the effectiveness of this part. We present an analytical model to predict message latency in multi-cluster systems in the presence of processor heterogeneity. The model is validated through comprehensive simulation, which demonstrates that the proposed model exhibits a good degree of accuracy for various system sizes and under different operating conditions.