One-dimensional polyelectrolyte/polymeric semiconductor core/shell structure : sulfonated poly(arylene ether ketone)/polyaniline nanofibers for organic field-effect transistors

A polyelectrolyte/polymeric semiconductor core/shell structure is developed for organic field-effect transistors (OFETs) based on sulfonated poly(arylene ether ketone)/polyaniline core/shell nanofibers via electrospinning and solution-phase selective polymerization. The polyelectrolyte does not work as a gate dielectric, but can provide an internal modulation from the nanointerface of the 1D core/shell nanostructure. The transistor devices display very high mobilities.

Graphene quantum dots directly generated from graphite via magnetron sputtering and the application in thin-film transistors

This work presents a novel method to prepare graphene quantum dots (GQDs) directly from graphite. A composite film of GQDs and ZnO was first prepared using the composite target of graphite and ZnO via magnetron sputtering, followed with hydrochloric acid treatment and dialysis. Morphology and optical properties of the GQDs were investigated using a number of techniques. The as-prepared GQDs are 4-12 nm in size and 1-2 nm in thickness. They also exhibited typical excitation-dependent properties as expected in carbon-based quantum dots. To demonstrate the potential applications of GQDs in electronic devices, pure ZnO and GQD-ZnO thin-film transistors (TFTs) using ZrOx dielectric were fabricated and examined. The ZnO TFT incorporating the GQDs exhibited enhanced performance: an on/off current ratio of 1.7 × 107, a field-effect mobility of 17.7 cm2/Vs, a subthreshold swing voltage of 90 mV/decade. This paper provides an efficient, reproducible and eco-friendly approach for the preparation of monodisperse GQDs directly from graphite. Our results suggest that GQDs fabricated using magnetron sputtering method may envision promising applications in electronic devices.

Au-doped polyacrylonitrile-polyaniline core-shell electrospun nanofibers having high field-effect mobilities

Au-doped polyacrylonitrile–polyaniline core–shell nanofibers are fabricated via electrospinning and subsequent gas-phase polymerization, providing a very high field-effect mobility of up to 11.6 cm² V⁻¹ s⁻¹. This method is also suitable for other conducting polymers and may eventually lead to a new and simplified fabrication of high-performance polymer organic field-effect transistors.

Simulation of a novel piezoelectric energy harvester

This paper focuses on a novel piezoelectric energy harvester for nanofiber PVDF to capture energy from vibration environment. A Resembling CMOS(R-CMOS) circuit consisting of two pMOS transistors and two nMOS transistors is presented, which can greatly increase the energy efficiency and reduce the power dissipation tremendously. Meanwhile, the novel harvester supplies smooth direct current. Simulation result of MULTISIM has shown that by using this novel piezoelectric energy harvester the input voltage (5v) can be rectified to be an output voltage (4.24v). The voltage conversion rate of the novel harvester is as high as 84.8% which is much larger than the rate of traditional rectifier circuit. Its potential application is in micro sensors, wireless transducers, and sensor networks.

Molecularly engineered graphene surfaces for sensing applications: A review.

Graphene is scientifically and commercially important because of its unique molecular structure which is monoatomic in thickness, rigorously two-dimensional and highly conjugated. Consequently, graphene exhibits exceptional electrical, optical, thermal and mechanical properties. Herein, we critically discuss the surface modification of graphene, the specific advantages that graphene-based materials can provide over other materials in sensor research and their related chemical and electrochemical properties. Furthermore, we describe the latest developments in the use of these materials for sensing technology, including chemical sensors and biosensors and their applications in security, environmental safety and diseases detection and diagnosis.

Applications of electrospun nanofibers for electronic devices

In recent decades, electrospinning of nanofibers has progressed very rapidly in both scientific and technological aspects, and electrospun nanofibers have shown enormous potential for various applications. In particular, electrospun nanofibers have significantly enhanced the application performance of many electronic devices, such as solar cells, mechanical-to-electric energy harvesters, rechargeable batteries, supercapacitors, sensors, field-effect transistors, diodes, photodetectors, and electrochromic devices. This chapter provides a comprehensive summary on the recent progress in the application of electrospun nanofibers in electronic devices.

Implementation of dual stack technique for reducing leakage and dynamic power

This paper deals with proposal of a new dual stack approach for reducing both leakage and dynamic powers. The development of digital integrated circuits is challenged by higher power consumption. Thecombination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Scaling improves transistor density and functionality ona chip. Scaling helps to increase speed and frequency of operation and hence higher performance. As voltages scale downward with the geometries threshold voltages must also decrease to gain the performance advantages of the new technology but leakage current increases exponentially. Today leakage power has become anincreasingly important issue in processor hardware and software design. It can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc. The leakage power increases astechnology is scaled down. In this paper, we propose a new dual stack approach for reducing both leakage and dynamic powers. Moreover, the novel dual stack approach shows the least speed power product whencompared to the existing methods. All well known approach is “Sleep” in this method we reduce leakage power. The proposed Dual Stack approach we reduce more power leakage. Dual Stack approach uses theadvantage of using the two extra pull-up and two extra pull-down transistors in sleep mode either in OFF state or in ON state. Since the Dual Stack portion can be made common to all logic circuitry, less number of transistors is needed to apply a certain logic circuit.The dual stack approach shows the least speed power product among all methods. The Dual Stack technique provides new ways to designers who require ultra-low leakage power consumption with much less speedpower product.