Design of a high sensitive double-gate field-effect transistor biosensor for DNA detection

The study of interactions between organic biomolecules and semiconducting surfaces is an important consideration for the design and fabrication of field-effect-transistor (FET) biosensor. This paper demonstrates DNA detection by employing a double-gate field effect transistor (DGFET). In addition, an investigation of sensitivity and signal to noise ratio (SNR) is carried out for different values of analyte concentration, buffer ion concentration, pH, reaction constant, etc. Sensitivity, which is indicated by the change of drain current, increases non-linearly after a specific value (∼1nM) of analyte concentration and decreases non-linearly with buffer ion concentration. However, sensitivity is linearly related to the fluidic gate voltage. The drain current has a significant effect on the positive surface group (-NH2) compared to the negative counterpart (-OH). Furthermore, the sensor has the same response at a particular value of pH (5.76) irrespective of the density of surface group, although it decreases with pH value. The signal to noise ratio is improved with higher analyte concentrations and receptor densities.

Performance analysis of a field-effect-transistor based aptasensor

Prostate cancer is one of the most diagnosed cancers which leads to a considerable number of deaths due to the lack of early and sensitive detection. This paper presents an aptamer functionalized field effect (FET) based biosensor for the detection of prostate cancer. Prostate specific antigen (PSA) is considered as the biomarker for prostate cancer whose detection is confirmed by attaching aptamers onto the sensor surface. Through the modelling and numerical simulation, the paper aims to evaluate and predict the performance parameters such as sensitivity, settling time, and limit of detection (LOD) of a label-free FET based electronic biosensor. Various sensor parameters such as structure (i.e., geometry), type of the FET (e.g., nanowire FET, spherical FET, ion-selective FET, and magnetic particle) radius of the FET channel and incubation time are optimized and analyzed. In addition, concentration of analyte biomolecules, diffusion coefficients and affinity to the receptor molecules are also investigated to determine the optimize performance parameters.

One-dimensional polyelectrolyte/polymeric semiconductor core/shell structure : sulfonated poly(arylene ether ketone)/polyaniline nanofibers for organic field-effect transistors

A polyelectrolyte/polymeric semiconductor core/shell structure is developed for organic field-effect transistors (OFETs) based on sulfonated poly(arylene ether ketone)/polyaniline core/shell nanofibers via electrospinning and solution-phase selective polymerization. The polyelectrolyte does not work as a gate dielectric, but can provide an internal modulation from the nanointerface of the 1D core/shell nanostructure. The transistor devices display very high mobilities.

Implementation of dual stack technique for reducing leakage and dynamic power

This paper deals with proposal of a new dual stack approach for reducing both leakage and dynamic powers. The development of digital integrated circuits is challenged by higher power consumption. Thecombination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Scaling improves transistor density and functionality ona chip. Scaling helps to increase speed and frequency of operation and hence higher performance. As voltages scale downward with the geometries threshold voltages must also decrease to gain the performance advantages of the new technology but leakage current increases exponentially. Today leakage power has become anincreasingly important issue in processor hardware and software design. It can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc. The leakage power increases astechnology is scaled down. In this paper, we propose a new dual stack approach for reducing both leakage and dynamic powers. Moreover, the novel dual stack approach shows the least speed power product whencompared to the existing methods. All well known approach is “Sleep” in this method we reduce leakage power. The proposed Dual Stack approach we reduce more power leakage. Dual Stack approach uses theadvantage of using the two extra pull-up and two extra pull-down transistors in sleep mode either in OFF state or in ON state. Since the Dual Stack portion can be made common to all logic circuitry, less number of transistors is needed to apply a certain logic circuit.The dual stack approach shows the least speed power product among all methods. The Dual Stack technique provides new ways to designers who require ultra-low leakage power consumption with much less speedpower product.