Numerical modeling of dual phase microstructure behavior under deformation conditions on the basis of digital material representation

Development of a digital material representation (DMR) model of dual phase steel is presented within the paper. Subsequent stages involving generation of a reliable representation of microstructure morphology, assignment of material properties to component phases and incorporation of the model into the commercial finite element software are described within the paper. Different approaches used to recreate dual phase morphology in a digital manner are critically assessed. However, particular attention is placed on innovative identification of phase properties at the micro scale by using micro-pillar compression tests. The developed DMR model is finally applied to model influence of micro scale features on failure initiation and propagation under loading conditions.

Strain gradients in Cu-Fe thin films and multilayers during micropillar compression

Plastic strain gradients can influence the work-hardening behaviour of metals due to the accumulation of geometrically necessary discolations at the micron/submicron scale. A finite element model based on the conventional theory of mechanism-based strain-gradient plasticity has been developed to simulate the micropillar compression of Cu–Fe thin films and multilayers. The modelling results show that the geometric constraints lead to inhomogeneous deformation in the Cu layers, which agrees well with the bulging of Cu layers observed experimentally. Plastic strain gradients develop inside the individual layers, leading to extra work-hardening due to the accumulation of geometrically necessary dislocations. In the multilayer specimens, the Cu layers deform more severely than the Fe layers, resulting in the development of tensile stresses in the Fe layers. It is proposed that these tensile stresses are responsible for the development of micro-cracks in the Fe layers.

Implementation of soft processor based SOC for JPEG compression on FPGA

With the advent of semiconductor process and EDA tools technology, IC designers can integrate more functions. However, to reduce the demand of time-to-market and tackle the increasing complexity of SoC, the need of fast prototyping and testing is growing. Taking advantage of deep submicron technology, modern FPGAs provide a fast and low-cost prototyping with large logic resources and high performance. So the hardware is mapped onto an emulation platform based on FPGA that mimics the behaviour of SOC. In this paper we use FPGA as a system on chip which is then used for image compression by 2-D DCT respectively and proposed SoC for image compression using soft core Microblaze. The JPEG standard defines compression techniques for image data. As a consequence, it allows to store and transfer image data with considerably reduced demand for storage space and bandwidth. From the four processes provided in the JPEG standard, only one, the baseline process is widely used. Proposed SoC for JPEG compression has been implemented on FPGA Spartan-6 SP605 evaluation board using Xilinx platform studio, because field programmable gate array have reconfigurable hardware architecture. Hence the JPEG image with high speed and reduced size can be obtained at low risk and low power consumption of about 0.699W. The proposed SoC for image compression is evaluated at 83.33MHz on Xilinx Spartan-6 FPGA.