Pullpipelining: A technique for systolic pipelined circuits

Pullpipelining, a pipeline technique where data is pulled from successor stages from predecessor stages is proposed Control circuits using a synchronous, a semi-synchronous and an asynchronous approach are given. Simulation examples for a DLX generic RISC datapath show that common control pipeline circuit overhead is avoided using the proposal. Applications to linear systolic arrays in cases when computation is finished at early stages in the array are foreseen. This would allow run-time data-driven digital frequency modulation of synchronous pipelined designs. This has applications to implement algorithms exhibiting average-case processing time using a synchronous approach.

Verification and FPGA circuits of a block-2 fast path-based predictor

This paper formally derives a new path-based neural branch prediction algorithm (FPP) into blocks of size two for a lower hardware solution while maintaining similar input-output characteristic to the algorithm. The blocked solution, here referred to as B2P algorithm, is obtained using graph theory and retiming methods. Verification approaches were exercised to show that prediction performances obtained from the FPP and B2P algorithms differ within one mis-prediction per thousand instructions using a known framework for branch prediction evaluation. For a chosen FPGA device, circuits generated from the B2P algorithm showed average area savings of over 25% against circuits for the FPP algorithm with similar time performances thus making the proposed blocked predictor superior from a practical viewpoint.

A clocking technique for FPGA pipelined designs

This paper presents a clocking pipeline technique referred to as a single-pulse pipeline (PP-Pipeline) and applies it to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). A PP-pipeline replicates the operation of asynchronous micropipelined control mechanisms using synchronous-orientated logic resources commonly found in FPGA devices. Consequently, circuits with an asynchronous-like pipeline operation can be efficiently synthesized using a synchronous design methodology. The technique can be extended to include data-completion circuitry to take advantage of variable data-completion processing time in synchronous pipelined designs. It is also shown that the PP-pipeline reduces the clock tree power consumption of pipelined circuits. These potential applications are demonstrated by post-synthesis simulation of FPGA circuits. (C) 2004 Elsevier B.V. All rights reserved.

Shared neural circuits for mentalizing about the self and others

Although many examples exist for shared neural representations of self and other, it is unknown how such shared representations interact with the rest of the brain. Furthermore, do high-level inference-based shared mentalizing representations interact with lower level embodied/simulation-based shared representations? We used functional neuroimaging (fMRI) and a functional connectivity approach to assess these questions during high-level inference-based mentalizing. Shared mentalizing representations in ventromedial prefrontal cortex, posterior cingulate/precuneus, and temporo-parietal junction (TPJ) all exhibited identical functional connectivity patterns during mentalizing of both self and other. Connectivity patterns were distributed across low-level embodied neural systems such as the frontal operculum/ventral premotor cortex, the anterior insula, the primary sensorimotor cortex, and the presupplementary motor area. These results demonstrate that identical neural circuits are implementing processes involved in mentalizing of both self and other and that the nature of such processes may be the integration of low-level embodied processes within higher level inference-based mentalizing.

Nitrogen recycling through the gut and the nitrogen economy of ruminants: An asynchronous symbiosis

The extensive development of the ruminant forestomach sets apart their N economy from that of nonruminants in a number of respects. Extensive pregastric fermentation alters the profile of protein reaching the small intestine, largely through the transformation of nitrogenous compounds into microbial protein. This process is fueled primarily by carbohydrate fermentation and includes extensive recycling of N between the body and gut lumen pools. Nitrogen recycling occurs via blood and gut lumen exchanges of urea and NH3, as well as endogenous gut and secretory N entry into the gut lumen, and the subsequent digestion and absorption of microbial and endogenous protein. Factors controlling urea transfer to the gut from blood, including the contributions of urea transporters, remain equivocal. Ammonia produced by microbial degradation of urea and dietary and endogenous AA is utilized by microbial fermentation or absorbed and primarily converted to urea. Therefore, microbial growth and carbohydrate fermentation affect the extent of NH3 absorption and urea N recycling and excretion. The extensive recycling of N to the rumen represents an evolutionary advantage of the ruminant in terms of absorbable protein supply during periods of dietary protein deficiency, or asynchronous carbohydrate and protein supply, but incurs a cost of greater N intakes, especially in terms of excess N excretion. Efforts to improve the efficiency of N utilization in ruminants by synchronizing fermentable energy and N availability have generally met with limited success with regards to production responses. In contrast, imposing asynchrony through oscillating dietary protein concentration, or infrequent supplementation, surprisingly has not negatively affected production responses unless the frequency of supplementation is less than once every 3 d. In some cases, oscillation of dietary protein concentration has improved N retention compared with animals fed an equal amount of dietary protein on a daily basis. This may reflect benefits of Orn cycle adaptations and sustained recycling of urea to the gut. The microbial symbiosis of the ruminant is inherently adaptable to asynchronous N and energy supply. Recycling of urea to the gut buffers the effect of irregular dietary N supply such that intuitive benefits of rumen synchrony in terms of the efficiency of N utilization are typically not observed in practice.

Web-based occupant feedback for building energy management systems using fuzzy logic

This paper describes the development and validation of a novel web-based interface for the gathering of feedback from building occupants about their environmental discomfort including signs of Sick Building Syndrome (SBS). The gathering of such feedback may enable better targeting of environmental discomfort down to the individual as well as the early detection and subsequently resolution by building services of more complex issues such as SBS. The occupant's discomfort is interpreted and converted to air-conditioning system set points using Fuzzy Logic. Experimental results from a multi-zone air-conditioning test rig have been included in this paper.

Investigation into low power of a 2D Inverse Discrete CosineTransform (IDCT) in FPGAs

Design for low power in FPGA is rather limited since technology factors affecting power are either fixed or limited for FPGA families. This paper investigates opportunities for power savings of a pipelined 2D IDCT design at the architecture and logic level. We report power consumption savings of over 25% achieved in FPGA circuits obtained from clock gating implementation of optimizations made at the algorithmic level(1).

Power performance with gated clocks of a pipelined Cordic Core

This paper presents the evaluation in power consumption of gated clocks pipelined circuits with different register configurations in Virtex-based FPGA devices. Power impact of a gated clock circuitry aimed at reducing flip-flops output rate at the bit level is studied. Power performance is also given for pipeline stages based on the implementation of a double edge-triggered flip-flop. Using a pipelined Cordic Core circuit as an example, this study did not find evidence in power benefits either when gated clock at the bit-level or double-edge triggered flip-flops used when synthesized with FPGA logic resources.

FPGA organization for the fast path-based neural branch predictor

This paper develops cycle-level FPGA circuits of an organization for a fast path-based neural branch predictor Our results suggest that practical sizes of prediction tables are limited to around 32 KB to 64 KB in current FPGA technology due mainly to FPGA area of logic resources to maintain the tables. However the predictor scales well in terms of prediction speed. Table sizes alone should not be used as the only metric for hardware budget when comparing neural-based predictor to predictors of totally different organizations. This paper also gives early evidence to shift the attention on to the recovery from mis-prediction latency rather than on prediction latency as the most critical factor impacting accuracy of predictions for this class of branch predictors.

Performance of asynchronous channel assignment scheme in non-uniform and dynamic topology WLANs

Dense deployments of wireless local area networks (WLANs) are fast becoming a permanent feature of all developed cities around the world. While this increases capacity and coverage, the problem of increased interference, which is exacerbated by the limited number of channels available, can severely degrade the performance of WLANs if an effective channel assignment scheme is not employed. In an earlier work, an asynchronous, distributed and dynamic channel assignment scheme has been proposed that (1) is simple to implement, (2) does not require any knowledge of the throughput function, and (3) allows asynchronous channel switching by each access point (AP). In this paper, we present extensive performance evaluation of this scheme when it is deployed in the more practical non-uniform and dynamic topology scenarios. Specifically, we investigate its effectiveness (1) when APs are deployed in a nonuniform fashion resulting in some APs suffering from higher levels of interference than others and (2) when APs are effectively switched `on/off' due to the availability/lack of traffic at different times, which creates a dynamically changing network topology. Simulation results based on actual WLAN topologies show that robust performance gains over other channel assignment schemes can still be achieved even in these realistic scenarios.

An asynchronous channel assignment scheme: performance evaluation

Due to its popularity, dense deployments of wireless local area networks (WLANs) are becoming a common feature of many cities around the world. However, with only a limited number of channels available, the problem of increased interference can severely degrade the performance of WLANs if an effective channel assignment scheme is not employed. In an earlier work, we proposed an improved asynchronous distributed and dynamic channel assignment scheme that (1) is simple to implement, (2) does not require any knowledge of the throughput function, and (3) allows asynchronous channel switching by each access point (AP). In this paper, we present extensive performance evaluation of the proposed scheme in practical scenarios found in densely populated WLAN deployments. Specifically, we investigate the convergence behaviour of the scheme and how its performance gains vary with different number of available channels and in different deployment densities. We also prove that our scheme is guaranteed to converge in a single iteration when the number of channels is greater than the number of neighbouring APs.