Dual carrier modulation soft demapper

An Orthogonal Frequency Division Multiplexing (OFDM) communication system with a transmitter and a receiver. The transmitter is arranged to transmit channel estimation sequences on each of a plurality of band groups, or bands, and to transmit data on each of the band groups or bands. The receiver is arranged to receive the channel estimation sequences for each band group or band to calculate channel state information from each of the channel estimation sequences transmitted on that band group or band and to form an average channel state information. The receiver receives the transmitted data, transforms the received data into the frequency domain, equalizes the received data using the channel state information, demaps the equalized data to re-construct the received data as soft bits and modifies the soft bits using the averaged channel state information.

Experiences applying OVM 2.0 to an 8B/10B RTL design

The SystemVerilog implementation of the Open Verification Methodology (OVM) is exercised on an 8b/10b RTL open core design in the hope of being a simple yet complete exercise to expose the key features of OVM. Emphasis is put onto the actual usage of the verification components rather than a complete verification flow aiming at being of help to readers unfamiliar with OVM seeking to apply the methodology to their own designs. A link that takes you to the complete code is given to reinforce this aim. We found the methodology easy to use but intimidating at first glance specially for someone with little experience in object oriented programming. However it is clear to see the flexibility, portability and reusability of verification code once you manage to give some first steps.

A Packet/Frame sync detector based on statistical mode with application to wireless-USB

Wireless Personal Area Networks (WPANs) are offering high data rates suitable for interconnecting high bandwidth personal consumer devices (Wireless HD streaming, Wireless-USB and Bluetooth EDR). ECMA-368 is the Physical (PHY) and Media Access Control (MAC) backbone of many of these wireless devices. WPAN devices tend to operate in an ad-hoc based network and therefore it is important to successfully latch onto the network and become part of one of the available piconets. This paper presents a new algorithm for detecting the Packet/Fame Sync (PFS) signal in ECMA-368 to identify piconets and aid symbol timing. The algorithm is based on correlating the received PFS symbols with the expected locally stored symbols over the 24 or 12 PFS symbols, but selecting the likely TFC based on the highest statistical mode from the 24 or 12 best correlation results. The results are very favorable showing an improvement margin in the order of 11.5dB in reference sensitivity tests between the required performance using this algorithm and the performance of comparable systems.

Functional verification: approaches and challenges

It's a fact that functional verification (FV) is paramount within the hardware's design cycle. With so many new techniques available today to help with FV, which techniques should we really use? The answer is not straightforward and is often confusing and costly. The tools and techniques to be used in a project have to be decided upon early in the design cycle to get the best value for these new verification methods. This paper gives a quick survey in the form of an overview on FV, establishes the difference between verification and validation, describes the bottlenecks that appear in the verification process, examines the challenges in FV and exposes the current FV technologies and trends.

Processing system accepting exceptional numbers

A processing system comprises: input means arranged to receive at least one input group of bits representing at least one respective input number; output means arranged to output at least one output group of bits representing at least one respective output number; and processing means arranged to perform an operation on the at least one input group of bits to produce the at least one output group of bits such that the at least one output number is related to the at least one input number by a mathematical operation; and wherein each of the numbers can be any of a set of numbers which includes a series of numbers, positive infinity, negative infinity and nullity.

A clocking technique with power savings in virtex-based pipelined designs

This paper presents the evaluation in power consumption of a clocking technique for pipelined designs. The technique shows a dynamic power consumption saving of around 30% over a conventional global clocking mechanism. The results were obtained from a series of experiments of a systolic circuit implemented in Virtex-II devices. The conversion from a global-clocked pipelined design to the proposed technique is straightforward, preserving the original datapath design. The savings can be used immediately either as a power reduction benefit or to increase the frequency of operation of a design for the same power consumption.

A n-Bit Reconfigurable Scalar Quantiser

A reconfigurable scalar quantiser capable of accepting n-bit input data is presented. The data length n can be varied in the range 1... N-1 under partial-run time reconfiguration, p-RTR. Issues as improvement in throughput using this reconfigurable quantiser of p-RTR against RTR for data of variable length are considered. The quantiser design referred to as the priority quantiser PQ is then compared against a direct design of the quantiser DIQ. It is then evaluated that for practical quantiser sizes, PQ shows better area usage when both are targeted onto the same FPGA. Other benefits are also identified.

Improving mW/MHz ratio in FPGAs pipelined designs

This paper presents a simple clocking technique to migrate classical synchronous pipelined designs to a synchronous functional-equivalent alternative system in the context of FPGAs. When the new pipelined design runs at the same throughput of the original design, around 30% better mW/MHz ratio was observed in Virtex-based FPGA circuits. The evaluation is done using a simple but representative and practical systolic design as an example. The technique in essence is a simple replacement of the clocking mechanism for the pipe-storage elements; however no extra design effort is needed. The results show that the proposed technique allows immediate power and area-time savings of existing designs rather than exploring potential benefits by a new logic design to the problem using the classic pipeline clocking mechanism.

Parallel pipelined array architectures for real-time histogram computation in consumer devices

The real-time parallel computation of histograms using an array of pipelined cells is proposed and prototyped in this paper with application to consumer imaging products. The array operates in two modes: histogram computation and histogram reading. The proposed parallel computation method does not use any memory blocks. The resulting histogram bins can be stored into an external memory block in a pipelined fashion for subsequent reading or streaming of the results. The array of cells can be tuned to accommodate the required data path width in a VLSI image processing engine as present in many imaging consumer devices. Synthesis of the architectures presented in this paper in FPGA are shown to compute the real-time histogram of images streamed at over 36 megapixels at 30 frames/s by processing in parallel 1, 2 or 4 pixels per clock cycle.

In vitro fermentation by human gut bacteria of proteolytically digested caseinomacropeptide nonenzymatically glycosylated with prebiotic carbohydrates

The in vitro fermentation selectivity of hydrolyzed caseinomacropeptide (CMP) glycosylated, via Maillard reaction (MR), with lactulose, galacto-oligosaccharides from lactose (GOSLa), and galacto-oligosaccharides from lactulose (GOSLu) was evaluated, using pH-controlled small-scale batch cultures at 37 °C under anaerobic conditions with human feces. After 10 and 24 h of fermentation, neoglyconjugates exerted a bifidogenic activity, similar to those of the corresponding prebiotic carbohydrates. No significant differences were found in Bacteroides, Lactobacillus�Enterococcus, Clostridium histolyticum subgroup, Atopobium and Clostridium coccoides�Eubacterium rectale populations. Concentrations of lactic acid and short-chain fatty acids (SCFA) produced during the fermentation of prebiotic carbohydrates were similar to those produced for their respective neoglycoconjugates at both fermentation times. These findings, joined with the functional properties attributed to CMP, could open up new applications of MR products involving prebiotics as novel multiple-functional ingredients with potential beneficial effects on human health.

In vitro fermentation of alternansucrase raffinose-derived oligosaccharides by human gut bacteria

In this work, in vitro fermentation of alternansucrase raffinose-derived oligosaccharides, previously fractionated according to their degree of polymerization (DP; from DP4 to DP10), was carried out using small-scale pH-controlled batch cultures at 37 °C under anaerobic conditions with human feces. Bifidogenic activity of oligosaccharides with DP4�6 similar to that of lactulose was observed; however, in general, a significant growth of lactic acid bacteria Bacteroides, Atopobium cluster, and Clostridium histolyticum group was not shown during incubation. Acetic acid was the main short chain fatty acid (SCFA) produced during the fermentation process; the highest levels of this acid were shown by alternansucrase raffinose acceptor pentasaccharides at 10 h (63.11 mM) and heptasaccharides at 24 h (54.71 mM). No significant differences between the gas volume produced by the mixture of raffinose-based oligosaccharides (DP5�DP10) and inulin after 24 h of incubation were detected, whereas lower gas volume was generated by DP4 oligosaccharides. These findings indicate that novel raffinose-derived oligosaccharides (DP4�DP10) could be a new source of prebiotic carbohydrates.