194 resultados para Space reconfiguration
Resumo:
Little has so far been reported on the robustness of non-orthogonal space-time block codes (NO-STBCs) over highly correlated channels (HCC). Some of the existing NO-STBCs are indeed weak in robustness against HCC. With a view to overcoming such a limitation, a generalisation of the existing robust NO-STBCs based on a 'matrix Alamouti (MA)' structure is presented.
Resumo:
One major assumption in all orthogonal space-time block coding (O-STBC) schemes is that the channel remains static over the entire length of the codeword. However, time selective fading channels do exist, and in such case the conventional O-STBC detectors can suffer from a large error floor in the high signal-to-noise ratio (SNR) cases. This paper addresses such an issue by introducing a parallel interference cancellation (PIC) based detector for the Gi coded systems (i=3 and 4).
Resumo:
All the orthogonal space-time block coding (O-STBC) schemes are based on the following assumption: the channel remains static over the entire length of the codeword. However, time selective fading channels do exist, and in many cases the conventional O-STBC detectors can suffer from a large error floor in the high signal-to-noise ratio (SNR) cases. This paper addresses such an issue by introducing a parallel interference cancellation (PIC) based detector for the Gi coded systems (i=3 and 4).
Resumo:
Several non-orthogonal space-time block coding (NO-STBC) schemes have recently been proposed to achieve full rate transmission. Some of these schemes, however, suffer from weak robustness: their channel matrices will become ill conditioned in the case of highly correlated channels (HCC). To address this issue, this paper derives a family of robust NO-STBC schemes for four Tx antennas based on the worst case of HCC. These codes turned out to be a superset of Jafarkhani's quasi-orthogonal STBC codes. A computationally affordable linear decoder is also proposed. Although these codes achieve a similar performance to the non-robust schemes under normal channel conditions, they offer a strong robustness against HCC (although possibly yielding a poorer performance). Finally, computer simulations are presented to verify the algorithm design.
Resumo:
The paper deals with an issue in space time block coding (STBC) design. It considers whether, over a time-selective channel, orthogonal STBC (O-STBC) or non-orthogonal STBC (NO-STBC) performs better. It is shown that, under time-selectiveness, once vehicle speed has risen above a certain value, NO-STBC always outperforms O-STBC across the whole SNR range. Also, considering that all existing NO-STBC schemes have been investigated under quasi-static channels only, a new simple receiver is derived for the NO-STBC system under time-selective channels.
Resumo:
This paper proposes the subspace-based space-time (ST) dual-rate blind linear detectors for synchronous DS/CDMA systems, which can be viewed as the ST extension of our previously presented purely temporal dual-rate blind linear detectors. The theoretical analyses on their performances are also carried out. Finally, the two-stage ST blind detectors are presented, which combine the adaptive purely temporal dual-rate blind MMSE filters with the non-adaptive beamformer. Their adaptive stages with parallel structure converge much faster than the corresponding adaptive ST dual-rate blind MMSE detectors, while having a comparable computational complexity to the latter.
Resumo:
Reconfigurable computing is becoming an important new alternative for implementing computations. Field programmable gate arrays (FPGAs) are the ideal integrated circuit technology to experiment with the potential benefits of using different strategies of circuit specialization by reconfiguration. The final form of the reconfiguration strategy is often non-trivial to determine. Consequently, in this paper, we examine strategies for reconfiguration and, based on our experience, propose general guidelines for the tradeoffs using an area-time metric called functional density. Three experiments are set up to explore different reconfiguration strategies for FPGAs applied to a systolic implementation of a scalar quantizer used as a case study. Quantitative results for each experiment are given. The regular nature of the example means that the results can be generalized to a wide class of industry-relevant problems based on arrays.