The irrelevant sound phenomenon revisited: what role for working memory capacity?

High-span individuals (as measured by the operation span [CSPAN] technique) are less likely than low-span individuals to notice their own names in an unattended auditory stream (A. R. A. Conway, N. Cowan, & M F. Bunting, 2001). The possibility that OSPAN accounts for individual differences in auditory distraction on an immediate recall test was examined. There was no evidence that high-OSPAN participants were more resistant to the disruption caused by irrelevant speech in serial or in free recall. Low-OSPAN participants did, however, make more semantically related intrusion errors from the irrelevant sound stream in a free recall test (Experiment 4). Results suggest that OSPAN mediates semantic components of auditory distraction dissociable from other aspects of the irrelevant sound effect.

Time-based prospective memory in children with autism spectrum disorder

In this study, for the first time, prospective memory was investigated in 11 school-aged children with autism spectrum disorders and 11 matched neurotypical controls. A computerised time-based prospective memory task was embedded in a visuospatial working memory test and required participants to remember to respond to certain target times. Controls had significantly more correct prospective memory responses than the autism spectrum group. Moreover, controls checked the time more often and increased time-monitoring more steeply as the target times approached. These differences in time-checking may suggest that prospective memory in autism spectrum disorders is affected by reduced self-initiated processing as indicated by reduced task monitoring.

Memory operations in rapid serial visual presentation

Short-term memory (STM) has often been considered to be a central resource in cognition. This study addresses its role in rapid serial visual presentation (RSVP) tasks tapping into temporal attention-the attentional blink (AB). Various STM operations are tested for their impact on performance and, in particular, on the AB. Memory tasks were found to exert considerable impact on general performance but the size of the AB was more or less immune to manipulations of STM load. Likewise, the AB was unaffected by manipulating the match between items held in STM and targets or temporally close distractors in the RSVP stream. The emerging picture is that STM resources, or their lack, play no role in the AB. Alternative accounts assuming serial consolidation, selection for action, and distractor-induced task-set interference are discussed.

Short-term memory and the attentional blink: capacity versus content

When people monitor the rapid serial visual presentation (RSVP) of stimuli for two targets (T1 and T2), they often miss T2 if it falls into a time window of about half a second after T1 onset, a phenomenon known as the attentional blink (AB). We found that overall performance in an RSVP task was impaired by a concurrent short-term memory (STM) task and, furthermore, that this effect increased when STM load was higher and when its content was more task relevant. Loading visually defined stimuli and adding articulatory suppression further impaired performance on the RSVP task, but the size of the AB over time (i.e., T1-T2 lag) remained unaffected by load or content. This suggested that at least part of the performance in an RSVP task reflects interference between competing codes within STM, as interference models have held, whereas the AB proper reflects capacity limitations in the transfer to STM, as consolidation models have claimed.

Verification and FPGA circuits of a block-2 fast path-based predictor

This paper formally derives a new path-based neural branch prediction algorithm (FPP) into blocks of size two for a lower hardware solution while maintaining similar input-output characteristic to the algorithm. The blocked solution, here referred to as B2P algorithm, is obtained using graph theory and retiming methods. Verification approaches were exercised to show that prediction performances obtained from the FPP and B2P algorithms differ within one mis-prediction per thousand instructions using a known framework for branch prediction evaluation. For a chosen FPGA device, circuits generated from the B2P algorithm showed average area savings of over 25% against circuits for the FPP algorithm with similar time performances thus making the proposed blocked predictor superior from a practical viewpoint.

A new organization for a perceptron-based branch predictor and its FPGA implementation

An unaltered rearrangement of the original computation of a neural based predictor at the algorithmic level is introduced as a new organization. Its FPGA implementation generates circuits that are 1.7 faster than a direct implementation of the original algorithm. This faster clock rate allows to implement predictors with longer history lengths using the nearly the same hardware budget.

FPGA organization for the fast path-based neural branch predictor

This paper develops cycle-level FPGA circuits of an organization for a fast path-based neural branch predictor Our results suggest that practical sizes of prediction tables are limited to around 32 KB to 64 KB in current FPGA technology due mainly to FPGA area of logic resources to maintain the tables. However the predictor scales well in terms of prediction speed. Table sizes alone should not be used as the only metric for hardware budget when comparing neural-based predictor to predictors of totally different organizations. This paper also gives early evidence to shift the attention on to the recovery from mis-prediction latency rather than on prediction latency as the most critical factor impacting accuracy of predictions for this class of branch predictors.

Efficient FPGA-based regular expression pattern matching

An approach to the automatic generation of efficient Field Programmable Gate Arrays (FPGAs) circuits for the Regular Expression-based (RegEx) Pattern Matching problems is presented. Using a novel design strategy, as proposed, circuits that are highly area-and-time-efficient can be automatically generated for arbitrary sets of regular expressions. This makes the technique suitable for applications that must handle very large sets of patterns at high speed, such as in the network security and intrusion detection application domains. We have combined several existing techniques to optimise our solution for such domains and proposed the way the whole process of dynamic generation of FPGAs for RegEX pattern matching could be automated efficiently.

Towards a developmental memory-based and embodied cognitive architecture

A novel memory-based embodied cognitive architecture is introduced – the MBC architecture. It is founded upon neuropsychological theory, and may be applied to investigating the interplay of embodiment, autonomy, and environmental interaction as related to the development of cognition.