Memory-based Embodied Cognition: a computational architecture

At its most fundamental, cognition as displayed by biological agents (such as humans) may be said to consist of the manipulation and utilisation of memory. Recent discussions in the field of cognitive robotics have emphasised the role of embodiment and the necessity of a value or motivation for autonomous behaviour. This work proposes a computational architecture – the Memory-Based Cognitive (MBC) architecture – based upon these considerations for the autonomous development of control of a simple mobile robot. This novel architecture will permit the exploration of theoretical issues in cognitive robotics and animal cognition. Furthermore, the biological inspiration of the architecture is anticipated to result in a mobile robot controller which displays adaptive behaviour in unknown environments.

A management architecture for active networks

In this paper we present an architecture for network and applications management, which is based on the Active Networks paradigm and shows the advantages of network programmability. The stimulus to develop this architecture arises from an actual need to manage a cluster of active nodes, where it is often required to redeploy network assets and modify nodes connectivity. In our architecture, a remote front-end of the managing entity allows the operator to design new network topologies, to check the status of the nodes and to configure them. Moreover, the proposed framework allows to explore an active network, to monitor the active applications, to query each node and to install programmable traps. In order to take advantage of the Active Networks technology, we introduce active SNMP-like MIBs and agents, which are dynamic and programmable. The programmable management agents make tracing distributed applications a feasible task. We propose a general framework that can inter-operate with any active execution environment. In this framework, both the manager and the monitor front-ends communicate with an active node (the Active Network Access Point) through the XML language. A gateway service performs the translation of the queries from XML to an active packet language and injects the code in the network. We demonstrate the implementation of an active network gateway for PLAN (Packet Language for Active Networks) in a forty active nodes testbed. Finally, we discuss an application of the active management architecture to detect the causes of network failures by tracing network events in time.

Wind turbine blade pitch control system

The present invention provides an improvement for a wind turbine (20) having at least one blade (21) mounted on a hub (22) for controlled rotation about a blade axis (yb-yb) to vary the pitch of the blade relative to an airstream. The hub is mounted on a nacelle (23) for rotation about a hub axis (xh-xh). The wind turbine includes a main pitch control system for selectively controlling the pitch of the blade, and/or a safety pitch control system for overriding the main blade pitch control system and for causing the blade to move toward a feathered position in the event of an overspeed or fault condition. The improvement includes: an energy storage device (26) mounted on the nacelle and associated with the blade; a pitch-axis controller (25) mounted on the nacelle and associated with the blade and with the energy storage device; an electro-mechanical actuator (28) mounted on the hub and associated with the blade; and at least one slip ring (29) operatively arranged to transmit power and/or data signals between the pitch-axis controller and the electro-mechanical actuator; whereby the mass on the rotating hub may be reduced.

Active networks: an evolution of the internet

Active Networks can be seen as an evolution of the classical model of packet-switched networks. The traditional and ”passive” network model is based on a static definition of the network node behaviour. Active Networks propose an “active” model where the intermediate nodes (switches and routers) can load and execute user code contained in the data units (packets). Active Networks are a programmable network model, where bandwidth and computation are both considered shared network resources. This approach opens up new interesting research fields. This paper gives a short introduction of Active Networks, discusses the advantages they introduce and presents the research advances in this field.

Verification and FPGA circuits of a block-2 fast path-based predictor

This paper formally derives a new path-based neural branch prediction algorithm (FPP) into blocks of size two for a lower hardware solution while maintaining similar input-output characteristic to the algorithm. The blocked solution, here referred to as B2P algorithm, is obtained using graph theory and retiming methods. Verification approaches were exercised to show that prediction performances obtained from the FPP and B2P algorithms differ within one mis-prediction per thousand instructions using a known framework for branch prediction evaluation. For a chosen FPGA device, circuits generated from the B2P algorithm showed average area savings of over 25% against circuits for the FPP algorithm with similar time performances thus making the proposed blocked predictor superior from a practical viewpoint.

FPGA organization for the fast path-based neural branch predictor

This paper develops cycle-level FPGA circuits of an organization for a fast path-based neural branch predictor Our results suggest that practical sizes of prediction tables are limited to around 32 KB to 64 KB in current FPGA technology due mainly to FPGA area of logic resources to maintain the tables. However the predictor scales well in terms of prediction speed. Table sizes alone should not be used as the only metric for hardware budget when comparing neural-based predictor to predictors of totally different organizations. This paper also gives early evidence to shift the attention on to the recovery from mis-prediction latency rather than on prediction latency as the most critical factor impacting accuracy of predictions for this class of branch predictors.

Experiences applying OVM 2.0 to an 8B/10B RTL design

The SystemVerilog implementation of the Open Verification Methodology (OVM) is exercised on an 8b/10b RTL open core design in the hope of being a simple yet complete exercise to expose the key features of OVM. Emphasis is put onto the actual usage of the verification components rather than a complete verification flow aiming at being of help to readers unfamiliar with OVM seeking to apply the methodology to their own designs. A link that takes you to the complete code is given to reinforce this aim. We found the methodology easy to use but intimidating at first glance specially for someone with little experience in object oriented programming. However it is clear to see the flexibility, portability and reusability of verification code once you manage to give some first steps.

Preliminary results from a real time control system using optical information

Successful results from training an adaptive controller to use optical information to balance an inverted pendulum are presented in comparison to the training requirements using traditional controller inputs. Results from research into the psychology of the sense of balance in humans are presented as the motivation for the investigation of this new type of controller. The simulated model of the inverted pendulum and the virtual reality environments used to provide the optical input are described The successful introduction of optical information is found to require the preservation of at least two of the traditional input types and entail increased training time for the adaptive controller and reduced performance (measured as the time the pendulum remains upright).

Results of applying sensor fusion to a control system using optic flow

The results from applying a sensor fusion process to an adaptive controller used to balance all inverted pendulum axe presented. The goal of the sensor fusion process was to replace some of the four mechanical measurements, which are known to be sufficient inputs for a linear state feedback controller to balance the system, with optic flow variables. Results from research into the psychology of the sense of balance in humans were the motivation for the investigation of this new type of controller input. The simulated model of the inverted pendulum and the virtual reality environments used to provide the optical input are described. The successful introduction of optical information is found to require the preservation of at least two of the traditional input types and entail increased training till-le for the adaptive controller and reduced performance (measured as the time the pendulum remains upright)

Efficient FPGA-based regular expression pattern matching

An approach to the automatic generation of efficient Field Programmable Gate Arrays (FPGAs) circuits for the Regular Expression-based (RegEx) Pattern Matching problems is presented. Using a novel design strategy, as proposed, circuits that are highly area-and-time-efficient can be automatically generated for arbitrary sets of regular expressions. This makes the technique suitable for applications that must handle very large sets of patterns at high speed, such as in the network security and intrusion detection application domains. We have combined several existing techniques to optimise our solution for such domains and proposed the way the whole process of dynamic generation of FPGAs for RegEX pattern matching could be automated efficiently.

Real-time context-aware network security policy enforcement system (RC-NSPES)

The major technical objectives of the RC-NSPES are to provide a framework for the concurrent operation of reactive and pro-active security functions to deliver efficient and optimised intrusion detection schemes as well as enhanced and highly correlated rule sets for more effective alerts management and root-cause analysis. The design and implementation of the RC-NSPES solution includes a number of innovative features in terms of real-time programmable embedded hardware (FPGA) deployment as well as in the integrated management station. These have been devised so as to deliver enhanced detection of attacks and contextualised alerts against threats that can arise from both the network layer and the application layer protocols. The resulting architecture represents an efficient and effective framework for the future deployment of network security systems.

'Flat phase' PID controllers

Flat Phase PID Controllers have the property that the phase of the transfer function round the associated feedback loop is constant or flat around the design frequency, with the aim that the phase margin and overshoot to a step response is unaffected when the gain of the device under control changes. Such designs have been achieved using Bode Integrals and by ensuring the phase is the same at two frequencies. This paper extends the ‘two frequency’ controller and describes a novel three frequency controller. The different design strategies arc compared.

Impedance control of redundant drive joints with double actuation

This paper proposes impedance control of redundant drive joints with double actuation (RDJ-DA) to produce compliant motions with the future goal of higher bandwidth. First, to reduce joint inertia, a double-input-single-output mechanism with one internal degree of freedom (DOF) is presented as part of the basic structure of the RDJ-DA. Next, the basic structure of RDJ-DA is further explained and its dynamics and statics are derived. Then, the impedance control scheme of RDJ-DA to produce compliant motions is proposed and the validity of the proposed controller is investigated using numerical examples.

A practical method for testing high-speed networking hardware architectures

This paper deals with the key issues encountered in testing during the development of high-speed networking hardware systems by documenting a practical method for "real-life like" testing. The proposed method is empowered by modern and commonly available Field Programmable Gate Array (FPGA) technology. Innovative application of standard FPGA blocks in combination with reconfigurability are used as a back-bone of the method. A detailed elaboration of the method is given so as to serve as a general reference. The method is fully characterised and compared to alternatives through a case study proving it to be the most efficient and effective one at a reasonable cost.

Multiple-model fault tolerant control of terminal unites of HVAC Systems

In this work, a fault-tolerant control scheme is applied to a air handling unit of a heating, ventilation and air-conditioning system. Using the multiple-model approach it is possible to identify faults and to control the system under faulty and normal conditions in an effective way. Using well known techniques to model and control the process, this work focuses on the importance of the cost function in the fault detection and its influence on the reconfigurable controller. Experimental results show how the control of the terminal unit is affected in the presence a fault, and how the recuperation and reconfiguration of the control action is able to deal with the effects of faults.