Multi-microprocessor control of processes with pure time delay

In 1967 a novel scheme was proposed for controlling processes with large pure time delay (Fellgett et al, 1967) and some of the constituent parts of the scheme were investigated (Swann, 1970; Atkinson et al, 1973). At that time the available computational facilities were inadequate for the scheme to be implemented practically, but with the advent of modern microcomputers the scheme becomes feasible. This paper describes recent work (Mitchell, 1987) in implementing the scheme in a new multi-microprocessor configuration and shows the improved performance it provides compared with conventional three-term controllers.

Optimum decision delay of the finite-length DFE

This work investigates the optimum decision delay and tap-length of the finite-length decision feedback equalizer. First we show that, if the feedback filter (FBF) length Nb is equal to or larger than the channel memory v and the decision delay Δ is smaller than the feedforward filter (FFF) length Nf, then only the first Δ+1 elements of the FFF can be nonzero. Based on this result we prove that the maximum effective FBF length is equal to the channel memory v, and if Nb ≥ v and Nf is long enough, the optimum decision delay that minimizes the MMSE is Nf-1.

An adaptive linear equalizer with optimum filter length and decision delay

The power of an adaptive equalizer is maximized when the structural parameters including the tap-length and decision delay can be optimally chosen. Although the method for adjusting either the tap-length or decision delay has been proposed, adjusting both simultaneously becomes much more involved as they interact with each other. In this paper, this problem is solved by putting a linear prewhitener before the equalizer, with which the equivalent channel becomes maximum-phase. This implies that the optimum decision delay can be simply ¯xed at the tap-length minus one, while the tap-length can then be chosen using a similar approach as that proposed in our previous work.

Switching on a two-dimensional time-harmonic scalar wave in the presence of a diffracting edge

This paper concerns the switching on of two-dimensional time-harmonic scalar waves. We first review the switch-on problem for a point source in free space, then proceed to analyse the analogous problem for the diffraction of a plane wave by a half-line (the ‘Sommerfeld problem’), determining in both cases the conditions under which the field is well-approximated by the solution of the corresponding frequency domain problem. In both cases the rate of convergence to the frequency domain solution is found to be dependent on the strength of the singularity on the leading wavefront. In the case of plane wave diffraction at grazing incidence the frequency domain solution is immediately attained along the shadow boundary after the arrival of the leading wavefront. The case of non-grazing incidence is also considered.

Code-switching and transfer: an exploration of similarities and differences

This handbook article gives an historical overview of the development of research into code-switching and discusses its relationship to other language contact phenomena.

Human-computer cooperative teleoperation with time delay

Presents a method for model based bilateral control of master-slave arm with time delay between master and slave arms, where the system supports cooperative action between manual and automatic modes. The method realises efficiencies in master-slave arm control with the simplicities of a computer and the flexibility of a skilled human operator.

A comparison between bond graphs switching modelling techniques implemented on a boost dc-dc converter

A Bond Graph is a graphical modelling technique that allows the representation of energy flow between the components of a system. When used to model power electronic systems, it is necessary to incorporate bond graph elements to represent a switch. In this paper, three different methods of modelling switching devices are compared and contrasted: the Modulated Transformer with a binary modulation ratio (MTF), the ideal switch element, and the Switched Power Junction (SPJ) method. These three methods are used to model a dc-dc Boost converter and then run simulations in MATLAB/SIMULINK. To provide a reference to compare results, the converter is also simulated using PSPICE. Both quantitative and qualitative comparisons are made to determine the suitability of each of the three Bond Graph switch models in specific power electronics applications

Performance analysis of data transmissions in MPLS and non-MPLS networks

Basic Network transactions specifies that datagram from source to destination is routed through numerous routers and paths depending on the available free and uncongested paths which results in the transmission route being too long, thus incurring greater delay, jitter, congestion and reduced throughput. One of the major problems of packet switched networks is the cell delay variation or jitter. This cell delay variation is due to the queuing delay depending on the applied loading conditions. The effect of delay, jitter accumulation due to the number of nodes along transmission routes and dropped packets adds further complexity to multimedia traffic because there is no guarantee that each traffic stream will be delivered according to its own jitter constraints therefore there is the need to analyze the effects of jitter. IP routers enable a single path for the transmission of all packets. On the other hand, Multi-Protocol Label Switching (MPLS) allows separation of packet forwarding and routing characteristics to enable packets to use the appropriate routes and also optimize and control the behavior of transmission paths. Thus correcting some of the shortfalls associated with IP routing. Therefore MPLS has been utilized in the analysis for effective transmission through the various networks. This paper analyzes the effect of delay, congestion, interference, jitter and packet loss in the transmission of signals from source to destination. In effect the impact of link failures, repair paths in the various physical topologies namely bus, star, mesh and hybrid topologies are all analyzed based on standard network conditions.