Improving mW/MHz ratio in FPGAs pipelined designs

This paper presents a simple clocking technique to migrate classical synchronous pipelined designs to a synchronous functional-equivalent alternative system in the context of FPGAs. When the new pipelined design runs at the same throughput of the original design, around 30% better mW/MHz ratio was observed in Virtex-based FPGA circuits. The evaluation is done using a simple but representative and practical systolic design as an example. The technique in essence is a simple replacement of the clocking mechanism for the pipe-storage elements; however no extra design effort is needed. The results show that the proposed technique allows immediate power and area-time savings of existing designs rather than exploring potential benefits by a new logic design to the problem using the classic pipeline clocking mechanism.

Active micromachined integrated terahertz circuits

Schottky barrier diodes have been integrated into on-chip rectangular waveguides. Two novel techniques have been developed to fabricate diodes with posts suitable for integration into waveguides. One technique produces diodes with anode diameters of the order of microns with post heights from 90 to 125 microns and the second technique produces sub-micron anodes with post heights around 20 microns. A method has been developed to incorporate these structures into a rectangular waveguide and provide a top contact onto the anode which could be used as an I.F. output in a mixer circuit. Devices have been fabricated and D.C. characterized.

Output envelope adjustment for an environmental fuzzy logic controller

A two-level fuzzy logic controller for use in air-conditioning systems is outlined in this paper. At the first level a simplified controller is produced from expert knowledge and envelope adjustment is introduced, while the second level provides a means for adapting this controller to different working spaces. The mechanism for adaption is easily implemented and can be used in real time. A series of simulations is presented to illustrate the proposed schema.

Quasi-decoupled fuzzy logic controller

The authors describe the design of a fuzzy logic controller for the control of a planar two-link manipulator. The plant is quasi-decoupled with respect to gravity. Complete decoupling is not achieved due to the nonoptimal nature of the expert rules. The performance of the fuzzy controller is compared to that of the critically damped computed torque controller. Results are presented complete with robustness tests.

Distributed fuzzy logic for building management systems using local operating networks

This paper describes the development of an experimental distributed fuzzy control system for heating and ventilation (HVAC) systems within a building. Each local control loop is affected by a number of local variables, as well as information from neighboring controllers. By including this additional information it is hoped that a more equal allocation of resources can be achieved.

Missing the logic of the text: Lord Butler’s report on intelligence on Iraqi weapons of mass destruction

This article focuses on the final report of Lord Butler’s review of British intelligence on weapons of mass destruction (WMD), specifically on its treatment of the accuracy of the use of intelligence on Iraqi WMD in a government dossier published in September 2002 ahead of the 2003 Iraq war. In the report, the demonstration of the accuracy of the “September Dossier” hinges on the insertion of tables that compare side-by-side quotations from this document and from intelligence assessments. The analysis of the textual and visual methods by which the report is written reveals how the logic of the comparative tables is missed in the Butler report: the logic of these tables requires that the comparison between quotations from the two documents should be performed at the level of their details but the Butler report performs its comparison only at a broad and general level.

Implementation of Parallel (p,q) Counters for High Speed Digital Multipliers

Both the (5,3) counter and (2,2,3) counter multiplication techniques are investigated for the efficiency of their operation speed and the viability of the architectures when implemented in a fast bipolar ECL technology. The implementation of the counters in series-gated ECL and threshold logic are contrasted for speed, noise immunity and complexity, and are critically compared with the fastest practical design of a full-adder. A novel circuit technique to overcome the problems of needing high fan-in input weights in threshold circuits through the use of negative weighted inputs is presented. The authors conclude that a (2,2,3) counter based array multiplier implemented in series-gated ECL should enable a significant increase in speed over conventional full adder based array multipliers.

Parallel Architectures for High Speed Multipliers

The authors compare various array multiplier architectures based on (p,q) counter circuits. The tradeoff in multiplier design is always between adding complexity and increasing speed. It is shown that by using a (2,2,3) counter cell it is possible to gain a significant increase in speed over a conventional full-adder, carry-save array based approach. The increase in complexity should be easily accommodated using modern emitter-coupled-logic processes.