The effect of Parkinson's disease on time estimation as a function of stimulus duration range and modality

The present research sought to investigate the role of the basal ganglia in timing of sub- and supra-second intervals via an examination of the ability of people with Parkinson's disease (PD) to make temporal judgments in two ranges, 100-500 ms, and 1-5 s. Eighteen nondemented medicated patients with PD were compared with 14 matched controls on a duration-bisection task in which participants were required to discriminate auditory and visual signal durations within each time range. Results showed that patients with PD exhibited more variable duration judgments across both signal modality and duration range than controls, although closer analyses confirmed a timing deficit in the longer duration range only. The findings presented here suggest the bisection procedure may be a useful tool in identifying timing impairments in PD and, more generally, reaffirm the hypothesised role of the basal ganglia in temporal perception at the level of the attentionally mediated internal clock as well as memory retrieval and/or decision-making processes. (c) 2007 Elsevier Inc. All rights reserved.

Investigation into low power of a 2D Inverse Discrete CosineTransform (IDCT) in FPGAs

Design for low power in FPGA is rather limited since technology factors affecting power are either fixed or limited for FPGA families. This paper investigates opportunities for power savings of a pipelined 2D IDCT design at the architecture and logic level. We report power consumption savings of over 25% achieved in FPGA circuits obtained from clock gating implementation of optimizations made at the algorithmic level(1).

Power performance with gated clocks of a pipelined Cordic Core

This paper presents the evaluation in power consumption of gated clocks pipelined circuits with different register configurations in Virtex-based FPGA devices. Power impact of a gated clock circuitry aimed at reducing flip-flops output rate at the bit level is studied. Power performance is also given for pipeline stages based on the implementation of a double edge-triggered flip-flop. Using a pipelined Cordic Core circuit as an example, this study did not find evidence in power benefits either when gated clock at the bit-level or double-edge triggered flip-flops used when synthesized with FPGA logic resources.

A new organization for a perceptron-based branch predictor and its FPGA implementation

An unaltered rearrangement of the original computation of a neural based predictor at the algorithmic level is introduced as a new organization. Its FPGA implementation generates circuits that are 1.7 faster than a direct implementation of the original algorithm. This faster clock rate allows to implement predictors with longer history lengths using the nearly the same hardware budget.

A clocking technique for FPGA pipelined designs

This paper presents a clocking pipeline technique referred to as a single-pulse pipeline (PP-Pipeline) and applies it to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). A PP-pipeline replicates the operation of asynchronous micropipelined control mechanisms using synchronous-orientated logic resources commonly found in FPGA devices. Consequently, circuits with an asynchronous-like pipeline operation can be efficiently synthesized using a synchronous design methodology. The technique can be extended to include data-completion circuitry to take advantage of variable data-completion processing time in synchronous pipelined designs. It is also shown that the PP-pipeline reduces the clock tree power consumption of pipelined circuits. These potential applications are demonstrated by post-synthesis simulation of FPGA circuits. (C) 2004 Elsevier B.V. All rights reserved.

Identification of nonlinear systems using generalized kernel models

Nonlinear system identification is considered using a generalized kernel regression model. Unlike the standard kernel model, which employs a fixed common variance for all the kernel regressors, each kernel regressor in the generalized kernel model has an individually tuned diagonal covariance matrix that is determined by maximizing the correlation between the training data and the regressor using a repeated guided random search based on boosting optimization. An efficient construction algorithm based on orthogonal forward regression with leave-one-out (LOO) test statistic and local regularization (LR) is then used to select a parsimonious generalized kernel regression model from the resulting full regression matrix. The proposed modeling algorithm is fully automatic and the user is not required to specify any criterion to terminate the construction procedure. Experimental results involving two real data sets demonstrate the effectiveness of the proposed nonlinear system identification approach.

A parallel convolutional coder including embedded puncturing with application to consumer devices

As consumers demand more functionality) from their electronic devices and manufacturers supply the demand then electrical power and clock requirements tend to increase, however reassessing system architecture can fortunately lead to suitable counter reductions. To maintain low clock rates and therefore reduce electrical power, this paper presents a parallel convolutional coder for the transmit side in many wireless consumer devices. The coder accepts a parallel data input and directly computes punctured convolutional codes without the need for a separate puncturing operation while the coded bits are available at the output of the coder in a parallel fashion. Also as the computation is in parallel then the coder can be clocked at 7 times slower than the conventional shift-register based convolutional coder (using DVB 7/8 rate). The presented coder is directly relevant to the design of modern low-power consumer devices

Humoral immunity following chickenpox is influenced by geography and ethnicity

Objectives To investigate the contribution of ethnicity and geographical location to varicella-zoster virus (VZV) serostatus and antibody concentrations. Methods The presence and concentrations of antibodies to VZV were measured in 639 Bangladeshi women born in Bangladesh (BBB), 94 Bangladeshi women born in the UK (BUK) and 262 White women born in the UK (WUK). The results were anaylsed in relation to demographic and social data. Results BBB women were significantly less likely to be VZV seropositive at all ages than both BUK and WUK women. However, the odds of a Bangladeshi-born woman being seropositive increased by 1.04 for each year under the age of 15 spent in the UK. In contrast, antibody concentrations were significantly lower in ethnic Bangladeshi women, irrespective of country of birth. White, but not Bangladeshi women, showed evidence of antibody boosting over time despite the latter having more exposure to children. Conclusion Geographical location during childhood is the major influence on age of primary infection with VZV while the level of antibody is related to ethnicity. Since the risk of re-infection with VZV following both natural infection and vaccination is increased as antibody concentrations fall, these results have implications for VZV vaccination programmes particularly in non-White populations.

Researcher development: the impact of undergraduate research opportunity programmes on students in the UK

Undergraduate research opportunity programmes (UROP) are common in North America where research has confirmed their benefits. These schemes are gaining ground in the UK, and this article provides evidence for how UK students are benefiting from the experience. Results suggest UROP makes a significant contribution to the research capabilities and confidence of participating students, boosting their understanding of both research and their own subjects. Whilst offering considerable benefits to student learning, there is no evidence that UROP schemes on their current small scale attract additional students to postgraduate research, since the majority that participate are already interested in postgraduate study. However, at an individual level, most students report increased confidence and appreciation of the realities of the research process, and desire to progress on to postgraduate study following the placement, indicating that schemes may have the potential to cultivate new research confidence and interest if expanded.

Farm productivity and efficiency in rural Bangladesh: the role of education revisited

This article reassesses the debate over the role of education in farm production in Bangladesh using a large dataset on rice producing households from 141 villages. Average and stochastic production frontier functions are estimated to ascertain the effect of education on productivity and efficiency. A full set of proxies for farm education stock variables are incorporated to investigate the ‘internal’ as well as ‘external’ returns to education. The external effect is investigated in the context of rural neighbourhoods. Our analysis reveals that in addition to raising rice productivity and boosting potential output, household education significantly reduces production inefficiencies. However, we are unable to find any evidence of the externality benefit of schooling – neighbour's education does not matter in farm production. We discuss the implication of these findings for rural education programmes in Bangladesh.

Identification of potential mechanisms of toxicity after di-(2-ethylhexyl)-phthalate (DEHP) adult exposure in the liver using a systems biology approach

Phthalates are industrial additives widely used as plasticizers. In addition to deleterious effects on male genital development, population studies have documented correlations between phthalates exposure and impacts on reproductive tract development and on the metabolic syndrome in male adults. In this work we investigated potential mechanisms underlying the impact of DEHP on adult mouse liver in vivo. A parallel analysis of hepatic transcript and metabolic profiles from adult mice exposed to varying DEHP doses was performed. Hepatic genes modulated by DEHP are predominantly PPARalpha targets. However, the induction of prototypic cytochrome P450 genes strongly supports the activation of additional NR pathways, including Constitutive Androstane Receptor (CAR). Integration of transcriptomic and metabonomic profiles revealed a correlation between the impacts of DEHP on genes and metabolites related to heme synthesis and to the Rev-erbalpha pathway that senses endogenous heme level. We further confirmed the combined impact of DEHP on the hepatic expression of Alas1, a critical enzyme in heme synthesis and on the expression of Rev-erbalpha target genes involved in the cellular clock and in energy metabolism. This work shows that DEHP interferes with hepatic CAR and Rev-erbalpha pathways which are both involved in the control of metabolism. The identification of these new hepatic pathways targeted by DEHP could contribute to metabolic and endocrine disruption associated with phthalate exposure. Gene expression profiles performed on microdissected testis territories displayed a differential responsiveness to DEHP. Altogether, this suggests that impacts of DEHP on adult organs, including testis, could be documented and deserve further investigations.

Parallel pipelined array architectures for real-time histogram computation in consumer devices

The real-time parallel computation of histograms using an array of pipelined cells is proposed and prototyped in this paper with application to consumer imaging products. The array operates in two modes: histogram computation and histogram reading. The proposed parallel computation method does not use any memory blocks. The resulting histogram bins can be stored into an external memory block in a pipelined fashion for subsequent reading or streaming of the results. The array of cells can be tuned to accommodate the required data path width in a VLSI image processing engine as present in many imaging consumer devices. Synthesis of the architectures presented in this paper in FPGA are shown to compute the real-time histogram of images streamed at over 36 megapixels at 30 frames/s by processing in parallel 1, 2 or 4 pixels per clock cycle.

PDM 2006: Proceedings of the International Workshop on Data Mining

Recently major processor manufacturers have announced a dramatic shift in their paradigm to increase computing power over the coming years. Instead of focusing on faster clock speeds and more powerful single core CPUs, the trend clearly goes towards multi core systems. This will also result in a paradigm shift for the development of algorithms for computationally expensive tasks, such as data mining applications. Obviously, work on parallel algorithms is not new per se but concentrated efforts in the many application domains are still missing. Multi-core systems, but also clusters of workstations and even large-scale distributed computing infrastructures provide new opportunities and pose new challenges for the design of parallel and distributed algorithms. Since data mining and machine learning systems rely on high performance computing systems, research on the corresponding algorithms must be on the forefront of parallel algorithm research in order to keep pushing data mining and machine learning applications to be more powerful and, especially for the former, interactive. To bring together researchers and practitioners working in this exciting field, a workshop on parallel data mining was organized as part of PKDD/ECML 2006 (Berlin, Germany). The six contributions selected for the program describe various aspects of data mining and machine learning approaches featuring low to high degrees of parallelism: The first contribution focuses the classic problem of distributed association rule mining and focuses on communication efficiency to improve the state of the art. After this a parallelization technique for speeding up decision tree construction by means of thread-level parallelism for shared memory systems is presented. The next paper discusses the design of a parallel approach for dis- tributed memory systems of the frequent subgraphs mining problem. This approach is based on a hierarchical communication topology to solve issues related to multi-domain computational envi- ronments. The forth paper describes the combined use and the customization of software packages to facilitate a top down parallelism in the tuning of Support Vector Machines (SVM) and the next contribution presents an interesting idea concerning parallel training of Conditional Random Fields (CRFs) and motivates their use in labeling sequential data. The last contribution finally focuses on very efficient feature selection. It describes a parallel algorithm for feature selection from random subsets. Selecting the papers included in this volume would not have been possible without the help of an international Program Committee that has provided detailed reviews for each paper. We would like to also thank Matthew Otey who helped with publicity for the workshop.

Maximising concurrency and scalability in a consistent, causal, distributed virtual reality system, whilst minimising the effect of network delays

The development of large scale virtual reality and simulation systems have been mostly driven by the DIS and HLA standards community. A number of issues are coming to light about the applicability of these standards, in their present state, to the support of general multi-user VR systems. This paper pinpoints four issues that must be readdressed before large scale virtual reality systems become accessible to a larger commercial and public domain: a reduction in the effects of network delays; scalable causal event delivery; update control; and scalable reliable communication. Each of these issues is tackled through a common theme of combining wall clock and causal time-related entity behaviour, knowledge of network delays and prediction of entity behaviour, that together overcome many of the effects of network delay.

Maximising concurrency and scalability in a consistent, causal, distributed virtual reality system, whilst minimising the effect of network delays

The development of large scale virtual reality and simulation systems have been mostly driven by the DIS and HLA standards community. A number of issues are coming to light about the applicability of these standards, in their present state, to the support of general multi-user VR systems. This paper pinpoints four issues that must be readdressed before large scale virtual reality systems become accessible to a larger commercial and public domain: a reduction in the effects of network delays; scalable causal event delivery; update control; and scalable reliable communication. Each of these issues is tackled through a common theme of combining wall clock and causal time-related entity behaviour, knowledge of network delays and prediction of entity behaviour, that together overcome many of the effects of network delays.