Implementation of Parallel (p,q) Counters for High Speed Digital Multipliers

Both the (5,3) counter and (2,2,3) counter multiplication techniques are investigated for the efficiency of their operation speed and the viability of the architectures when implemented in a fast bipolar ECL technology. The implementation of the counters in series-gated ECL and threshold logic are contrasted for speed, noise immunity and complexity, and are critically compared with the fastest practical design of a full-adder. A novel circuit technique to overcome the problems of needing high fan-in input weights in threshold circuits through the use of negative weighted inputs is presented. The authors conclude that a (2,2,3) counter based array multiplier implemented in series-gated ECL should enable a significant increase in speed over conventional full adder based array multipliers.

Parallel Architectures for High Speed Multipliers

The authors compare various array multiplier architectures based on (p,q) counter circuits. The tradeoff in multiplier design is always between adding complexity and increasing speed. It is shown that by using a (2,2,3) counter cell it is possible to gain a significant increase in speed over a conventional full-adder, carry-save array based approach. The increase in complexity should be easily accommodated using modern emitter-coupled-logic processes.

Western Chess: Zugzwang data

This data is derived from Eugene Nalimov's Depth-to-Mate Endgame Tables for Western Chess. While having the move is normally advantageous, there are positions where the side-to-move would have a better theoretical result if it were the other side to move. These are (Type A) 'zugzwang' positions where the 'obligation to act' is unwelcome. This data provides lists of all zugzwangs in sub-7-man chess, and summary data about those sets of zugzwangs including exemplar zugzwangs of maximum depth.