Decimal Multiplication using compact BCD Multiplier

Decimal multiplication is an integral part offinancial, commercial, and internet-based computations. The basic building block of a decimal multiplier is a single digit multiplier. It accepts two Binary Coded Decimal (BCD) inputs and gives a product in the range [0, 81] represented by two BCD digits. A novel design for single digit decimal multiplication that reduces the critical path delay and area is proposed in this research. Out of the possible 256 combinations for the 8-bit input, only hundred combinations are valid BCD inputs. In the hundred valid combinations only four combinations require 4 x 4 multiplication, combinations need x multiplication, and the remaining combinations use either x or x 3 multiplication. The proposed design makes use of this property. This design leads to more regular VLSI implementation, and does not require special registers for storing easy multiples. This is a fully parallel multiplier utilizing only combinational logic, and is extended to a Hex/Decimal multiplier that gives either a decimal output or a binary output. The accumulation ofpartial products generated using single digit multipliers is done by an array of multi-operand BCD adders for an (n-digit x n-digit) multiplication.

Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

High performance, low latency double digit decimal multiplier on ASIC and FPGA

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.

A Study of Single Stage Semi‐Dry Anaerobic Digestion of Organic Fraction of Municipal Solid Waste

Solid waste generation is a natural consequence of human activity and is increasing along with population growth, urbanization and industrialization. Improper disposal of the huge amount of solid waste seriously affects the environment and contributes to climate change by the release of greenhouse gases. Practicing anaerobic digestion (AD) for the organic fraction of municipal solid waste (OFMSW) can reduce emissions to environment and thereby alleviate the environmental problems together with production of biogas, an energy source, and digestate, a soil amendment. The amenability of substrate for biogasification varies from substrate to substrate and different environmental and operating conditions such as pH, temperature, type and quality of substrate, mixing, retention time etc. Therefore, the purpose of this research work is to develop feasible semi-dry anaerobic digestion process for the treatment of OFMSW from Kerala, India for potential energy recovery and sustainable waste management. This study was carried out in three phases in order to reach the research purpose. In the first phase, batch study of anaerobic digestion of OFMSW was carried out for 100 days at 32°C (mesophilic digestion) for varying substrate concentrations. The aim of this study was to obtain the optimal conditions for biogas production using response surface methodology (RSM). The parameters studied were initial pH, substrate concentration and total organic carbon (TOC). The experimental results showed that the linear model terms of initial pH and substrate concentration and the quadratic model terms of the substrate concentration and TOC had significant individual effect (p < 0.05) on biogas yield. However, there was no interactive effect between these variables (p > 0.05). The optimum conditions for maximizing the biogas yield were a substrate concentration of 99 g/l, an initial pH of 6.5 and TOC of 20.32 g/l. AD of OFMSW with optimized substrate concentration of 99 g/l [Total Solid (TS)-10.5%] is a semi-dry digestion system .Under the optimized condition, the maximum biogas yield was 53.4 L/kg VS (volatile solid).. In the second phase, semi-dry anaerobic digestion of organic solid wastes was conducted for 45 days in a lab-scale batch experiment for substrate concentration of 100 g/l (TS-11.2%) for investigating the start-up performances under thermophilic condition (50°C). The performance of the reactor was evaluated by measuring the daily biogas production and calculating the degradation of total solids and the total volatile solids. The biogas yield at the end of the digestion was 52.9 L/kg VS for the substrate concentration of 100 g/l. About 66.7% of volatile solid degradation was obtained during the digestion. A first order model based on the availability of substrate as the limiting factor was used to perform the kinetic studies of batch anaerobic digestion system. The value of reaction rate constant, k, obtained was 0.0249 day-1. A laboratory bench scale reactor with a capacity of 36.8 litres was designed and fabricated to carry out the continuous anaerobic digestion of OFMSW in the third phase. The purpose of this study was to evaluate the performance of the digester at total solid concentration of 12% (semi-dry) under mesophlic condition (32°C). The digester was operated with different organic loading rates (OLRs) and constant retention time. The performance of the reactor was evaluated using parameters such as pH, volatile fatty acid (VFA), alkalinity, chemical oxygen demand (COD), TOC and ammonia-N as well as biogas yield. During the reactor’s start-up period, the process is stable and there is no inhibition occurred and the average biogas production was 14.7 L/day. The reactor was fed in continuous mode with different OLRs (3.1,4.2 and 5.65 kg VS/m3/d) at constant retention time of 30 days. The highest volatile solid degradation of 65.9%, with specific biogas production of 368 L/kg VS fed was achieved with OLR of 3.1 kg VS/m3/d. Modelling and simulation of anaerobic digestion of OFMSW in continuous operation is done using adapted Anaerobic Digestion Model No 1 (ADM1).The proposed model, which has 34 dynamic state variables, considers both biochemical and physicochemical processes and contains several inhibition factors including three gas components. The number of processes considered is 28. The model is implemented in Matlab® version 7.11.0.584(R2010b). The model based on adapted ADM1 was tested to simulate the behaviour of a bioreactor for the mesophilic anaerobic digestion of OFMSW at OLR of 3.1 kg VS/m3/d. ADM1 showed acceptable simulating results.