Design and synthesis of efficient mac architectures for high speed decimal processor

Most of the commercial and financial data are stored in decimal fonn. Recently, support for decimal arithmetic has received increased attention due to the growing importance in financial analysis, banking, tax calculation, currency conversion, insurance, telephone billing and accounting. Performing decimal arithmetic with systems that do not support decimal computations may give a result with representation error, conversion error, and/or rounding error. In this world of precision, such errors are no more tolerable. The errors can be eliminated and better accuracy can be achieved if decimal computations are done using Decimal Floating Point (DFP) units. But the floating-point arithmetic units in today's general-purpose microprocessors are based on the binary number system, and the decimal computations are done using binary arithmetic. Only few common decimal numbers can be exactly represented in Binary Floating Point (BF P). ln many; cases, the law requires that results generated from financial calculations performed on a computer should exactly match with manual calculations. Currently many applications involving fractional decimal data perform decimal computations either in software or with a combination of software and hardware. The performance can be dramatically improved by complete hardware DFP units and this leads to the design of processors that include DF P hardware.VLSI implementations using same modular building blocks can decrease system design and manufacturing cost. A multiplexer realization is a natural choice from the viewpoint of cost and speed.This thesis focuses on the design and synthesis of efficient decimal MAC (Multiply ACeumulate) architecture for high speed decimal processors based on IEEE Standard for Floating-point Arithmetic (IEEE 754-2008). The research goal is to design and synthesize deeimal'MAC architectures to achieve higher performance.Efficient design methods and architectures are developed for a high performance DFP MAC unit as part of this research.

An efficient scheme for the evaluation of coding performance of high speed links incorporating joint error behaviour based on Monte Carlo Method

While channel coding is a standard method of improving a system’s energy efficiency in digital communications, its practice does not extend to high-speed links. Increasing demands in network speeds are placing a large burden on the energy efficiency of high-speed links and render the benefit of channel coding for these systems a timely subject. The low error rates of interest and the presence of residual intersymbol interference (ISI) caused by hardware constraints impede the analysis and simulation of coded high-speed links. Focusing on the residual ISI and combined noise as the dominant error mechanisms, this paper analyses error correlation through concepts of error region, channel signature, and correlation distance. This framework provides a deeper insight into joint error behaviours in high-speed links, extends the range of statistical simulation for coded high-speed links, and provides a case against the use of biased Monte Carlo methods in this setting

A Triple-Mode Feed-Forward Sigma-Delta Modulator Design For Gsm / Wcdma / Wlan Applications

This paper presents a cascaded 2-2-2 reconfigurable sigma-delta modulator that can handle GSM, WCDMA and WLAN standards. The modulator makes use of a low-distortion swing suppression topology which is highly suitable for wide band applications. In GSM mode, only the first stage (2nd order Σ-Δ ADC) is turned on to achieve 88dB dynamic range with oversampling ratio of 160 for a bandwidth of 200KHz; in WCDMA mode a 2-2 cascaded structure (4th order) is turned on with 1-bit in the first stage and 2-bit in the second stage to achieve 74 dB dynamic range with oversampling ratio of 16 for a bandwidth of 2MHz and a 2-2-2 cascaded MASH architecture with a 4-bit in the last stage to achieve a dynamic range of 58dB for a bandwidth of 20MHz. The novelty lies in the fact that unused blocks of second and third stages can be switched off taking into considerations like power consumption. The modulator is designed in TSMC 0.18um CMOS technology and operates at 1.8 supply voltage.

Health, Education and Employment in a Forward-Backward Dichotomy Based on Standard of Living Index for the Tribes in Kerala

The Paper unfolds the paradox that exists in the tribal community with respect to the development indicators and hence tries to cull out the difference in the standard of living of the tribes in a dichotomous framework, forward and backward. Four variables have been considered for ascertaining the standard of living and socio-economic conditions of the tribes. The data for the study is obtained from a primary survey in the three tribal predominant districts of Wayanad, Idukki and Palakkad. Wayanad was selected for studying six tribal communities (Paniya, Adiya, Kuruma, Kurichya, Urali and Kattunaika), Idukki for two communities (Malayarayan and Muthuvan) and Palakkad for one community (Irula). 500 samples from 9 prominent tribal communities of Kerala have been collected according to multistage proportionate random sample framework. The analysis highlights the disproportionate nature of socio-economic indicators within the tribes in Kerala owing to the failure of governmental schemes and assistances meant for their empowerment. The socio-economic variables, such as education, health, and livelihood have been augmented with SLI based on correlation analysis gives interesting inference for policy options as high educated tribal communities are positively correlated with high SLI and livelihood. Further, each of the SLI variable is decomposed using Correlation and Correspondence analysis for understanding the relative standing of the nine tribal sub communities in the three dimensional framework of high, medium and low SLI levels. Tribes with good education and employment (Malayarayan, Kuruma and Kurichya) have a better living standard and hence they can generally be termed as forward tribes whereas those with a low or poor education, employment and living standard indicators (Paniya, Adiya, Urali, Kattunaika, Muthuvans and Irula) are categorized as backward tribes