Long period gratings in multimode optical fibers: application in chemical sensing

We propose and demonstrate a new technique for evanescent wave chemical sensing by writing long period gratings in a bare multimode plastic clad silica fiber. The sensing length of the present sensor is only 10 mm, but is as sensitive as a conventional unclad evanescent wave sensor having about 100 mm sensing length. The minimum measurable concentration of the sensor reported here is 10 nmol/l and the operating range is more than 4 orders of magnitude. Moreover, the detection is carried out in two independent detection configurations viz., bright field detection scheme that detects the core-mode power and dark field detection scheme that detects the cladding mode power. The use of such a double detection scheme definitely enhances the reliability and accuracy of the results. Furthermore, the cladding of the present fiber need not be removed as done in conventional evanescent wave fiber sensors.

Soliton Resonances in Helium Films

The phenomenon of two-soliton resonances of the Kadomtsev-Petviashvilli equation for the superfluid surface density fluctuation in He films is studied. The velocity of the resonant soliton is obtained.

Solitons and their resonances on two-dimensional superfluid films

The dynamics of saturated two-dimensional superfluid4He films is shown to be governed by the Kadomtsev-Petviashvili equation with negative dispersion. It is established that the phenomena of soliton resonance could be observed in such films. Under the lowest order nonlinearity, such resonance would happen only if two dimensional effects are taken into account. The amplitude and velocity of the resonant soliton are obtained.

Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

High performance, low latency double digit decimal multiplier on ASIC and FPGA

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.