3 resultados para atomic clock
em Cochin University of Science
Resumo:
In the present thesis we have formulated the Dalgarno-Lewis procedure for two-and three-photon processes and an elegant alternate expressions are derived. Starting from a brief review on various multiphoton processes we have discussed the difficulties coming in the perturbative treatment of multiphoton processes. A small discussion on various available methods for studying multiphoton processes are presented in chapter 2. These theoretical treatments mainly concentrate on the evaluation of the higher order matrix elements coming in the perturbation theory. In chapter 3 we have described the use of Dalgarno-Lewis procedure and its implimentation on second order matrix elements. The analytical expressions for twophoton transition amplitude, two-photon ionization cross section, dipole dynamic polarizability and Kramers-Heiseberg are obtained in a unified manner. Fourth chapter is an extension of the implicit summation technique presented in chapter 3. We have clearly mentioned the advantage of our method, especially the analytical continuation of the relevant expressions suited for various values of radiation frequency which is also used for efficient numerical analysis. A possible extension of the work is to study various multiphoton processcs from the stark shifted first excited states of hydrogen atom. We can also extend this procedure for studying multiphoton processes in alkali atoms as well as Rydberg atoms. Also, instead of going for analytical expressions, one can try a complete numerical evaluation of the higher order matrix elements using this procedure.
Resumo:
Present work deals with the Preparation and characterization of high-k aluminum oxide thin films by atomic layer deposition for gate dielectric applications.The ever-increasing demand for functionality and speed for semiconductor applications requires enhanced performance, which is achieved by the continuous miniaturization of CMOS dimensions. Because of this miniaturization, several parameters, such as the dielectric thickness, come within reach of their physical limit. As the required oxide thickness approaches the sub- l nm range, SiO 2 become unsuitable as a gate dielectric because its limited physical thickness results in excessive leakage current through the gate stack, affecting the long-term reliability of the device. This leakage issue is solved in the 45 mn technology node by the integration of high-k based gate dielectrics, as their higher k-value allows a physically thicker layer while targeting the same capacitance and Equivalent Oxide Thickness (EOT). Moreover, Intel announced that Atomic Layer Deposition (ALD) would be applied to grow these materials on the Si substrate. ALD is based on the sequential use of self-limiting surface reactions of a metallic and oxidizing precursor. This self-limiting feature allows control of material growth and properties at the atomic level, which makes ALD well-suited for the deposition of highly uniform and conformal layers in CMOS devices, even if these have challenging 3D topologies with high aspect-ratios. ALD has currently acquired the status of state-of-the-art and most preferred deposition technique, for producing nano layers of various materials of technological importance. This technique can be adapted to different situations where precision in thickness and perfection in structures are required, especially in the microelectronic scenario.