Fixed Point Decimal Multiplication Using RPS Algorithm

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. A novel design for single digit decimal multiplication that reduces the critical path delay and area for an iterative multiplier is proposed in this research. The partial products are generated using single digit multipliers, and are accumulated based on a novel RPS algorithm. This design uses n single digit multipliers for an n × n multiplication. The latency for the multiplication of two n-digit Binary Coded Decimal (BCD) operands is (n + 1) cycles and a new multiplication can begin every n cycle. The accumulation of final partial products and the first iteration of partial product generation for next set of inputs are done simultaneously. This iterative decimal multiplier offers low latency and high throughput, and can be extended for decimal floating-point multiplication.

Recycling of NR Based Cured Latex Material Reclaimed with 2,2'-Dibenzamidodiphenyldisulphide in a TruckTire Tread Compound

It is observed that reclamation of natural rubber latex based rubber using 2,2'-dibenzamidodiphenvldisulphide as reclaiming agent is an optional methodology for recycling of waste latex rubber (WLR). For progressive replacement of virgin natural rubber by the reclaim, two alternatives curing system were investigated: adjustment or reduction of the curing system with increasing reclaim content, to compensate for the extra amount of curatives brought along by the reclaim. For fixed curing system, as if the reclaim were equivalent to virgin NR. The cure behavior, final crosslink density and distribution, mechanical properties, and dynamic viscoelastic properties of the blends with reclaimed WLR are measured and compared with the virgin compound. The morphology of the blends, sulfur migration, and final distribution are analyzed.The mechanical and dynamic viscoelastic properties deteriorate for both curing systems, but to a lesser extent for fixed curing system compared to adjusted curing system. With the fixed cure system, many properties like tensile strength and compression set do still deteriorate, but tan 6 and Mrrr„/Murxr, representative for the rolling resistance of tires are improved. On the other hand, with the adjusted cure system both mechanical and dynamic properties still deteriorate.

Design and synthesis of efficient mac architectures for high speed decimal processor

Most of the commercial and financial data are stored in decimal fonn. Recently, support for decimal arithmetic has received increased attention due to the growing importance in financial analysis, banking, tax calculation, currency conversion, insurance, telephone billing and accounting. Performing decimal arithmetic with systems that do not support decimal computations may give a result with representation error, conversion error, and/or rounding error. In this world of precision, such errors are no more tolerable. The errors can be eliminated and better accuracy can be achieved if decimal computations are done using Decimal Floating Point (DFP) units. But the floating-point arithmetic units in today's general-purpose microprocessors are based on the binary number system, and the decimal computations are done using binary arithmetic. Only few common decimal numbers can be exactly represented in Binary Floating Point (BF P). ln many; cases, the law requires that results generated from financial calculations performed on a computer should exactly match with manual calculations. Currently many applications involving fractional decimal data perform decimal computations either in software or with a combination of software and hardware. The performance can be dramatically improved by complete hardware DFP units and this leads to the design of processors that include DF P hardware.VLSI implementations using same modular building blocks can decrease system design and manufacturing cost. A multiplexer realization is a natural choice from the viewpoint of cost and speed.This thesis focuses on the design and synthesis of efficient decimal MAC (Multiply ACeumulate) architecture for high speed decimal processors based on IEEE Standard for Floating-point Arithmetic (IEEE 754-2008). The research goal is to design and synthesize deeimal'MAC architectures to achieve higher performance.Efficient design methods and architectures are developed for a high performance DFP MAC unit as part of this research.

Studies On Thermoplastic Elastomers With Special Reference To Triblock Copolymers And Nbr/Pvc Blends

Thermoplastic elastomers are a relatively new class of materials which compete with thermoset rubbers in some areas and thermoplastic materials in other areas. The main thrust of the present investigation is a comparative study’ on commercially .available triblock. styrene thermoplastic elastomers and those derived from blends of acrylonitrile-butadiene rubber and poly(vinyl chloride). The styrene—based thermoplastic elastomers are gaining acceptance as a replacement for both natural and synthetic rubber‘ in many‘ applications. TPEs based on blends of elastomers and plastics ix: the fastest growing segment of the broad class of thermoplastic elastomers. Broad applicability and simple technology of production are the attractive features of this class of TPES. NBR/PVC thermoplastic elastomers were selected for this investigation due to the versatility of PVC, its number one position, low cost. ability to Ina compounded into various flexible and rigid form with good physical and chemical and weathering properties etc., which will be passed over to PVC blends especially NBR/PVC blends which are known to form miscible systems

Design of Cyclophanes: Synthesis and Study of Photophysical and Biomolecular Recognition Properties

Development of organic molecules that exhibit selective interactions with different biomolecules has immense significance in biochemical and medicinal applications. In this context, our main objective has been to design a few novel functionaIized molecules that can selectively bind and recognize nucleotides and DNA in the aqueous medium through non-covalent interactions. Our strategy was to design novel cycIophane receptor systems based on the anthracene chromophore linked through different bridging moieties and spacer groups. It was proposed that such systems would have a rigid structure with well defined cavity, wherein the aromatic chromophore can undergo pi-stacking interactions with the guest molecules. The viologen and imidazolium moieties have been chosen as bridging units, since such groups, can in principle, could enhance the solubility of these derivatives in the aqueous medium as well as stabilize the inclusion complexes through electrostatic interactions.We synthesized a series of water soluble novel functionalized cyclophanes and have investigated their interactions with nucleotides, DNA and oligonucIeotides through photophysical. chiroptical, electrochemical and NMR techniques. Results indicate that these systems have favorable photophysical properties and exhibit selective interactions with ATP, GTP and DNA involving electrostatic. hydrophobic and pi-stacking interactions inside the cavity and hence can have potential use as probes in biology.

Studies in the geometry of the discrete plane

This thesis is an attempt to initiate the development of a discrete geometry of the discrete plane H = {(qmxo,qnyo); m,n e Z - the set of integers}, where q s (0,1) is fixed and (xO,yO) is a fixed point in the first quadrant of the complex plane, xo,y0 ¢ 0. The discrete plane was first considered by Harman in 1972, to evolve a discrete analytic function theory for geometric difference functions. We shall mention briefly, through various sections, the principle of discretization, an outline of discrete a alytic function theory, the concept of geometry of space and also summary of work done in this thesis

High performance, low latency double digit decimal multiplier on ASIC and FPGA

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.