Development of a varactor -controlled dual-frequency reconfigurable microstrip antenna

A new design for a compact electronically reconffgurable singlefeed dual frequency dual-polarized operation of a square-microstrip antenna capable of achieving tunable frequency ratios in the range 1.1 to 1.37 is proposed and experimentally studied. Varactor diodes inlegruted with the arms of the hexagonal slot and embedded in the square patch are used to tune the operating frequencies by applying reverse-bias voltage. The design has the advantage of size reduction up to 73.21% and 49.86% for the two resonant frequencies, respectively, as compared to standard rectangular patches. The antenna offers good bandwidth of 5.74% and 5.36% for the two operating frequencies. A highly simplified tuning circuitry without any transmission lines adds to the compactness of the design

A Compact Electronically Reconfigurable Dual Frequency Microstrip Antenna for L-Band Applications

A novel design of a computer electronically reconfigurable dual frequency dual polarized single feed hexagonal slot loaded microstrip antenna in L-band is introduced in this chapter. pin diodes are used to switch the operating frequencies considerably without much affecting the radiation characteristics and gain. the antenna can work with a frequency ratio varying in the wide range from 1.2 to 1.4. the proposed design has an added advantage of size reduction up to 72.21% and 46.84% for the two resonating frequencies compared to standard rectangular patches. the design also gives considerable bandwidth of up to 2.82% and 2.42 % for the operating frequencies.

Indian Mathematics Related to Architecture and Other Areas With Special Reference to Kerala

Department of Mathematics, Cochin University of Science and Technology

Design of Compact Reconfigurable Dual Frequency Microstrip Antennas Using Varactor Diodes

The design of a compact, single feed, dual frequency dual polarized and electronically reconfigurable microstrip antenna is presented in this paper. A square patch loaded with a hexagonal slot having extended slot arms constitutes the fundamental structure of the antenna. The tuning of the two resonant frequencies is realized by varying the effective electrical length of the slot arms by embedding varactor diodes across the slots. A high tuning range of 34.43% (1.037–1.394 GHz) and 9.27% (1.359–1.485 GHz) is achieved for the two operating frequencies respectively, when the bias voltage is varied from 0 to −30 V. The salient feature of this design is that it uses no matching networks even though the resonant frequencies are tuned in a wide range with good matching below −10 dB. The antenna has an added advantage of size reduction up to 80.11% and 65.69% for the two operating frequencies compared to conventional rectangular patches.

C-shaped slot loaded reconfigurable microstrip antenna

A new electronically reconfigurable dual frequency microstrip patch antenna with highly simplified varactor tuning circuitry is presented. The proposed design allows relatively independent selection of the two operating frequencies. Tuning ranges of 7.1 and 4.1% are realised for the two resonant frequencies without the use of any matching circuits.

Investigations on Reconfigurable Dual Frequency Microstrip Antennas Controlled by PIN Diodes and Varactors

In this work,we investigate novel designs of compact electronically reconfigurable dual frequency microstrip antennas with a single feed,operating mainly in L-band,without using any matching networks and complicated biasing circuitry.These antennas have been designed to operate in very popular frequency range where a great number of wireless communication applications exist.Efforts were carried out to introduce a successful,low cost reconfigurable dual-frequency microstrip antenna design to the wireless and radio frequency design community.

An Error-Localization, Validation and Optimization Tool for Embedded Code Augmentation: an Architecture Oriented Approach

Embedded systems are usually designed for a single or a specified set of tasks. This specificity means the system design as well as its hardware/software development can be highly optimized. Embedded software must meet the requirements such as high reliability operation on resource-constrained platforms, real time constraints and rapid development. This necessitates the adoption of static machine codes analysis tools running on a host machine for the validation and optimization of embedded system codes, which can help meet all of these goals. This could significantly augment the software quality and is still a challenging field.Embedded systems are usually designed for a single or a specified set of tasks. This specificity means the system design as well as its hardware/software development can be highly optimized. Embedded software must meet the requirements such as high reliability operation on resource-constrained platforms, real time constraints and rapid development. This necessitates the adoption of static machine codes analysis tools running on a host machine for the validation and optimization of embedded system codes, which can help meet all of these goals. This could significantly augment the software quality and is still a challenging field.Embedded systems are usually designed for a single or a specified set of tasks. This specificity means the system design as well as its hardware/software development can be highly optimized. Embedded software must meet the requirements such as high reliability operation on resource-constrained platforms, real time constraints and rapid development. This necessitates the adoption of static machine codes analysis tools running on a host machine for the validation and optimization of embedded system codes, which can help meet all of these goals. This could significantly augment the software quality and is still a challenging field.Embedded systems are usually designed for a single or a specified set of tasks. This specificity means the system design as well as its hardware/software development can be highly optimized. Embedded software must meet the requirements such as high reliability operation on resource-constrained platforms, real time constraints and rapid development. This necessitates the adoption of static machine codes analysis tools running on a host machine for the validation and optimization of embedded system codes, which can help meet all of these goals. This could significantly augment the software quality and is still a challenging field.This dissertation contributes to an architecture oriented code validation, error localization and optimization technique assisting the embedded system designer in software debugging, to make it more effective at early detection of software bugs that are otherwise hard to detect, using the static analysis of machine codes. The focus of this work is to develop methods that automatically localize faults as well as optimize the code and thus improve the debugging process as well as quality of the code.Validation is done with the help of rules of inferences formulated for the target processor. The rules govern the occurrence of illegitimate/out of place instructions and code sequences for executing the computational and integrated peripheral functions. The stipulated rules are encoded in propositional logic formulae and their compliance is tested individually in all possible execution paths of the application programs. An incorrect sequence of machine code pattern is identified using slicing techniques on the control flow graph generated from the machine code.An algorithm to assist the compiler to eliminate the redundant bank switching codes and decide on optimum data allocation to banked memory resulting in minimum number of bank switching codes in embedded system software is proposed. A relation matrix and a state transition diagram formed for the active memory bank state transition corresponding to each bank selection instruction is used for the detection of redundant codes. Instances of code redundancy based on the stipulated rules for the target processor are identified.This validation and optimization tool can be integrated to the system development environment. It is a novel approach independent of compiler/assembler, applicable to a wide range of processors once appropriate rules are formulated. Program states are identified mainly with machine code pattern, which drastically reduces the state space creation contributing to an improved state-of-the-art model checking. Though the technique described is general, the implementation is architecture oriented, and hence the feasibility study is conducted on PIC16F87X microcontrollers. The proposed tool will be very useful in steering novices towards correct use of difficult microcontroller features in developing embedded systems.

RNS based programmable multi-mode decimation filter for WCDMA and WiMAX

The recent trends envisage multi-standard architectures as a promising solution for the future wireless transceivers to attain higher system capacities and data rates. The computationally intensive decimation filter plays an important role in channel selection for multi-mode systems. An efficient reconfigurable implementation is a key to achieve low power consumption. To this end, this paper presents a dual-mode Residue Number System (RNS) based decimation filter which can be programmed for WCDMA and 802.16e standards. Decimation is done using multistage, multirate finite impulse response (FIR) filters. These FIR filters implemented in RNS domain offers high speed because of its carry free operation on smaller residues in parallel channels. Also, the FIR filters exhibit programmability to a selected standard by reconfiguring the hardware architecture. The total area is increased only by 24% to include WiMAX compared to a single mode WCDMA transceiver. In each mode, the unused parts of the overall architecture is powered down and bypassed to attain power saving. The performance of the proposed decimation filter in terms of critical path delay and area are tabulated.

Dual-mode RNS based programmable decimation filter for WCDMA and WLANa

The recent trends envisage multi-standard architectures as a promising solution for the future wireless transceivers. The computationally intensive decimation filter plays an important role in channel selection for multi-mode systems. An efficient reconfigurable implementation is a key to achieve low power consumption. To this end, this paper presents a dual-mode Residue Number System (RNS) based decimation filter which can be programmed for WCDMA and 802.11a standards. Decimation is done using multistage, multirate finite impulse response (FIR) filters. These FIR filters implemented in RNS domain offers high speed because of its carry free operation on smaller residues in parallel channels. Also, the FIR filters exhibit programmability to a selected standard by reconfiguring the hardware architecture. The total area is increased only by 33% to include WLANa compared to a single mode WCDMA transceiver. In each mode, the unused parts of the overall architecture is powered down and bypassed to attain power saving. The performance of the proposed decimation filter in terms of critical path delay and area are tabulated

A Generic Software Architecture for a Domain Specific Distributed Embedded System

In this paper, we have evolved a generic software architecture for a domain specific distributed embedded system. The system under consideration belongs to the Command, Control and Communication systems domain. The systems in such domain have very long operational lifetime. The quality attributes of these systems are equally important as the functional requirements. The main guiding principle followed in this paper for evolving the software architecture has been functional independence of the modules. The quality attributes considered most important for the system are maintainability and modifiability. Architectural styles best suited for the functionally independent modules are proposed with focus on these quality attributes. The software architecture for the system is envisioned as a collection of architecture styles of the functionally independent modules identified

A Multi-Mode Sigma-Delta ADC for GSM/WCDMA/ WLAN Applications

The demand for new telecommunication services requiring higher capacities, data rates and different operating modes have motivated the development of new generation multi-standard wireless transceivers. In multistandard design, sigma-delta based ADC is one of the most popular choices. To this end, in this paper we present cascaded 2-2-2 reconfigurable sigma-delta modulator that can handle GSM, WCDMA and WLAN standards. The modulator makes use of a low-distortion swing suppression topology which is highly suitable for wide band applications. In GSM mode, only the first stage (2nd order Σ-Δ ADC) is used to achieve a peak SNDR of 88dB with oversampling ratio of 160 for a bandwidth of 200KHz and for WCDMA mode a 2-2 cascaded structure (4th order) is turned on with 1-bit in the first stage and 2-bit in the second stage to achieve 74 dB peak SNDR with over-sampling ratio of 16 for a bandwidth of 2MHz. Finally, a 2-2-2 cascaded MASH architecture with 4-bit in the last stage is proposed to achieve a peak SNDR of 58dB for WLAN for a bandwidth of 20MHz. The novelty lies in the fact that unused blocks of second and third stages can be made inactive to achieve low power consumption. The modulator is designed in TSMC 0.18um CMOS technology and operates at 1.8 supply voltage

A Triple-Mode Feed-Forward Sigma-Delta Modulator Design For Gsm / Wcdma / Wlan Applications

This paper presents a cascaded 2-2-2 reconfigurable sigma-delta modulator that can handle GSM, WCDMA and WLAN standards. The modulator makes use of a low-distortion swing suppression topology which is highly suitable for wide band applications. In GSM mode, only the first stage (2nd order Σ-Δ ADC) is turned on to achieve 88dB dynamic range with oversampling ratio of 160 for a bandwidth of 200KHz; in WCDMA mode a 2-2 cascaded structure (4th order) is turned on with 1-bit in the first stage and 2-bit in the second stage to achieve 74 dB dynamic range with oversampling ratio of 16 for a bandwidth of 2MHz and a 2-2-2 cascaded MASH architecture with a 4-bit in the last stage to achieve a dynamic range of 58dB for a bandwidth of 20MHz. The novelty lies in the fact that unused blocks of second and third stages can be switched off taking into considerations like power consumption. The modulator is designed in TSMC 0.18um CMOS technology and operates at 1.8 supply voltage.

A Hybrid Architecture for Recognising Speech Signals in Malayalam

Speech is the primary, most prominent and convenient means of communication in audible language. Through speech, people can express their thoughts, feelings or perceptions by the articulation of words. Human speech is a complex signal which is non stationary in nature. It consists of immensely rich information about the words spoken, accent, attitude of the speaker, expression, intention, sex, emotion as well as style. The main objective of Automatic Speech Recognition (ASR) is to identify whatever people speak by means of computer algorithms. This enables people to communicate with a computer in a natural spoken language. Automatic recognition of speech by machines has been one of the most exciting, significant and challenging areas of research in the field of signal processing over the past five to six decades. Despite the developments and intensive research done in this area, the performance of ASR is still lower than that of speech recognition by humans and is yet to achieve a completely reliable performance level. The main objective of this thesis is to develop an efficient speech recognition system for recognising speaker independent isolated words in Malayalam.