Development of a varactor -controlled dual-frequency reconfigurable microstrip antenna

A new design for a compact electronically reconffgurable singlefeed dual frequency dual-polarized operation of a square-microstrip antenna capable of achieving tunable frequency ratios in the range 1.1 to 1.37 is proposed and experimentally studied. Varactor diodes inlegruted with the arms of the hexagonal slot and embedded in the square patch are used to tune the operating frequencies by applying reverse-bias voltage. The design has the advantage of size reduction up to 73.21% and 49.86% for the two resonant frequencies, respectively, as compared to standard rectangular patches. The antenna offers good bandwidth of 5.74% and 5.36% for the two operating frequencies. A highly simplified tuning circuitry without any transmission lines adds to the compactness of the design

A Compact Electronically Reconfigurable Dual Frequency Microstrip Antenna for L-Band Applications

A novel design of a computer electronically reconfigurable dual frequency dual polarized single feed hexagonal slot loaded microstrip antenna in L-band is introduced in this chapter. pin diodes are used to switch the operating frequencies considerably without much affecting the radiation characteristics and gain. the antenna can work with a frequency ratio varying in the wide range from 1.2 to 1.4. the proposed design has an added advantage of size reduction up to 72.21% and 46.84% for the two resonating frequencies compared to standard rectangular patches. the design also gives considerable bandwidth of up to 2.82% and 2.42 % for the operating frequencies.

Design of Compact Reconfigurable Dual Frequency Microstrip Antennas Using Varactor Diodes

The design of a compact, single feed, dual frequency dual polarized and electronically reconfigurable microstrip antenna is presented in this paper. A square patch loaded with a hexagonal slot having extended slot arms constitutes the fundamental structure of the antenna. The tuning of the two resonant frequencies is realized by varying the effective electrical length of the slot arms by embedding varactor diodes across the slots. A high tuning range of 34.43% (1.037–1.394 GHz) and 9.27% (1.359–1.485 GHz) is achieved for the two operating frequencies respectively, when the bias voltage is varied from 0 to −30 V. The salient feature of this design is that it uses no matching networks even though the resonant frequencies are tuned in a wide range with good matching below −10 dB. The antenna has an added advantage of size reduction up to 80.11% and 65.69% for the two operating frequencies compared to conventional rectangular patches.

C-shaped slot loaded reconfigurable microstrip antenna

A new electronically reconfigurable dual frequency microstrip patch antenna with highly simplified varactor tuning circuitry is presented. The proposed design allows relatively independent selection of the two operating frequencies. Tuning ranges of 7.1 and 4.1% are realised for the two resonant frequencies without the use of any matching circuits.

Investigations on Reconfigurable Dual Frequency Microstrip Antennas Controlled by PIN Diodes and Varactors

In this work,we investigate novel designs of compact electronically reconfigurable dual frequency microstrip antennas with a single feed,operating mainly in L-band,without using any matching networks and complicated biasing circuitry.These antennas have been designed to operate in very popular frequency range where a great number of wireless communication applications exist.Efforts were carried out to introduce a successful,low cost reconfigurable dual-frequency microstrip antenna design to the wireless and radio frequency design community.

A reconfiguration dual-frequency slot-loaded microstrip antenna controlled by pin diodes

A novel reconfigurable, single feed, dual frequency, dualpolarized operation of a hexagonal slot-loaded square mwrostrip antenna is presented in this paper. A pin diode incorporated in the slot is used to switch the two operating frequencies considerably, without significantly affecting the radiation characteristics and gain. The proposed antenna provides a size reduction up to 61% and 26% Jor the two resonating frequencies, compared to standard rectangular patches. This design also gives considerable bandwidth up to 3.3% and 4.27%, for the two frequencies with a low operating frequency ratio

Design Techniques for Sigmadelta based ADC for Wireless Applications

Analog-to digital Converters (ADC) have an important impact on the overall performance of signal processing system. This research is to explore efficient techniques for the design of sigma-delta ADC,specially for multi-standard wireless tranceivers. In particular, the aim is to develop novel models and algorithms to address this problem and to implement software tools which are avle to assist the designer's decisions in the system-level exploration phase. To this end, this thesis presents a framework of techniques to design sigma-delta analog to digital converters.A2-2-2 reconfigurable sigma-delta modulator is proposed which can meet the design specifications of the three wireless communication standards namely GSM,WCDMA and WLAN. A sigma-delta modulator design tool is developed using the Graphical User Interface Development Environment (GUIDE) In MATLAB.Genetic Algorithm(GA) based search method is introduced to find the optimum value of the scaling coefficients and to maximize the dynamic range in a sigma-delta modulator.

Efficient Transmitter/Receiver Architectures for High Performance Wireless Applications

The thesis focuses on efficient design methods and reconfiguration architectures suitable for higher performance wireless communication .The work presented in this thesis describes the development of compact,inexpensive and low power communication devices that are robust,testable and capable of handling multiple communication standards.A new multistandard Decimation Filter Design Toolbox is developed in MATLAB GUIDE environment.RNS based dual-mode decimation filters reconfigurable for WCDMA/WiMAX and WCDMA/WLANa standards are designed and implemented.It offers high speed operation with lesser area requirement and lower dynamic power dissipation.A novel sigma-delta based direct analog-to-residue converter that reduces the complexity of RNS conversion circuitry is presented.The performance of an OFDM communication system with a new RRNS-convolutional concatenated coding is analysed and improved BER performance is obtained under different channel conditions. Easily testable MAC units for filters are presented using Reed-Muller logic for realization.

Design and Development of re configurable compact cross patch antenna for switchable polarization

Antennas are necessary and vital components of communication and radar systems, but sometimes their inability to adjust to new operating scenarios can limit system performance. Reconfigurable antennas can adjust with changing system requirements or environmental conditions and provide additional levels of functionality that may result in wider instantaneous frequency bandwidths, more extensive scan volumes, and radiation patterns with more desirable side lobe distributions. Their agility and diversity created new horizons for different types of applications especially in cognitive radio, Multiple Input Multiple Output Systems, satellites and many other applications. Reconfigurable antennas satisfy the requirements for increased functionality, such as direction finding, beam steering, radar, control and command, within a confined volume. The intelligence associated with the reconfigurable antennas revolved around switching mechanisms utilized. In the present work, we have investigated frequency reconfigurable polarization diversity antennas using two methods: 1. By using low-loss, high-isolation switches such as PIN diode, the antenna can be structurally reconfigured to maintain the elements near their resonant dimensions for different frequency bands and/or polarization. 2. Secondly, the incorporation of variable capacitors or varactors, to overcome many problems faced in using switches and their biasing. The performances of these designs have been studied using standard simulation tools used in industry/academia and they have been experimentally verified. Antenna design guidelines are also deduced by accounting the resonances. One of the major contributions of the thesis lies in the analysis of the designed antennas using FDTD based numerical computation to validate their performance.

RNS based programmable multi-mode decimation filter for WCDMA and WiMAX

The recent trends envisage multi-standard architectures as a promising solution for the future wireless transceivers to attain higher system capacities and data rates. The computationally intensive decimation filter plays an important role in channel selection for multi-mode systems. An efficient reconfigurable implementation is a key to achieve low power consumption. To this end, this paper presents a dual-mode Residue Number System (RNS) based decimation filter which can be programmed for WCDMA and 802.16e standards. Decimation is done using multistage, multirate finite impulse response (FIR) filters. These FIR filters implemented in RNS domain offers high speed because of its carry free operation on smaller residues in parallel channels. Also, the FIR filters exhibit programmability to a selected standard by reconfiguring the hardware architecture. The total area is increased only by 24% to include WiMAX compared to a single mode WCDMA transceiver. In each mode, the unused parts of the overall architecture is powered down and bypassed to attain power saving. The performance of the proposed decimation filter in terms of critical path delay and area are tabulated.

Dual-mode RNS based programmable decimation filter for WCDMA and WLANa

The recent trends envisage multi-standard architectures as a promising solution for the future wireless transceivers. The computationally intensive decimation filter plays an important role in channel selection for multi-mode systems. An efficient reconfigurable implementation is a key to achieve low power consumption. To this end, this paper presents a dual-mode Residue Number System (RNS) based decimation filter which can be programmed for WCDMA and 802.11a standards. Decimation is done using multistage, multirate finite impulse response (FIR) filters. These FIR filters implemented in RNS domain offers high speed because of its carry free operation on smaller residues in parallel channels. Also, the FIR filters exhibit programmability to a selected standard by reconfiguring the hardware architecture. The total area is increased only by 33% to include WLANa compared to a single mode WCDMA transceiver. In each mode, the unused parts of the overall architecture is powered down and bypassed to attain power saving. The performance of the proposed decimation filter in terms of critical path delay and area are tabulated

A Multi-Mode Sigma-Delta ADC for GSM/WCDMA/ WLAN Applications

The demand for new telecommunication services requiring higher capacities, data rates and different operating modes have motivated the development of new generation multi-standard wireless transceivers. In multistandard design, sigma-delta based ADC is one of the most popular choices. To this end, in this paper we present cascaded 2-2-2 reconfigurable sigma-delta modulator that can handle GSM, WCDMA and WLAN standards. The modulator makes use of a low-distortion swing suppression topology which is highly suitable for wide band applications. In GSM mode, only the first stage (2nd order Σ-Δ ADC) is used to achieve a peak SNDR of 88dB with oversampling ratio of 160 for a bandwidth of 200KHz and for WCDMA mode a 2-2 cascaded structure (4th order) is turned on with 1-bit in the first stage and 2-bit in the second stage to achieve 74 dB peak SNDR with over-sampling ratio of 16 for a bandwidth of 2MHz. Finally, a 2-2-2 cascaded MASH architecture with 4-bit in the last stage is proposed to achieve a peak SNDR of 58dB for WLAN for a bandwidth of 20MHz. The novelty lies in the fact that unused blocks of second and third stages can be made inactive to achieve low power consumption. The modulator is designed in TSMC 0.18um CMOS technology and operates at 1.8 supply voltage

A Triple-mode Sigma-delta Modulator Design for Wireless Standards

This work presents a triple-mode sigma-delta modulator for three wireless standards namely GSM/WCDMA and Bluetooth. A reconfigurable ADC has been used to meet the wide bandwidth and high dynamic range requirements of the multi-standard receivers with less power consumption. A highly linear sigma-delta ADC which has reduced sensitivity to circuit imperfections has been chosen in our design. This is particularly suitable for wide band applications where the oversampling ratio is low. Simulation results indicate that the modulator achieves a peak SNDR of 84/68/68 dB over a bandwidth of 0.2/3.84/1.5 MHz with an oversampling ratio 128/8/8 in GSM/WCDMA/Bluetooth modes respectively

A Triple-Mode Feed-Forward Sigma-Delta Modulator Design For Gsm / Wcdma / Wlan Applications

This paper presents a cascaded 2-2-2 reconfigurable sigma-delta modulator that can handle GSM, WCDMA and WLAN standards. The modulator makes use of a low-distortion swing suppression topology which is highly suitable for wide band applications. In GSM mode, only the first stage (2nd order Σ-Δ ADC) is turned on to achieve 88dB dynamic range with oversampling ratio of 160 for a bandwidth of 200KHz; in WCDMA mode a 2-2 cascaded structure (4th order) is turned on with 1-bit in the first stage and 2-bit in the second stage to achieve 74 dB dynamic range with oversampling ratio of 16 for a bandwidth of 2MHz and a 2-2-2 cascaded MASH architecture with a 4-bit in the last stage to achieve a dynamic range of 58dB for a bandwidth of 20MHz. The novelty lies in the fact that unused blocks of second and third stages can be switched off taking into considerations like power consumption. The modulator is designed in TSMC 0.18um CMOS technology and operates at 1.8 supply voltage.

APSYM 2014

14th Biennial International Symposium on Antennas and propagation Department of Electronics, Cochin University of Science & Technology, Cochin 682022, INDIA