Decimal Multiplication using compact BCD Multiplier

Decimal multiplication is an integral part offinancial, commercial, and internet-based computations. The basic building block of a decimal multiplier is a single digit multiplier. It accepts two Binary Coded Decimal (BCD) inputs and gives a product in the range [0, 81] represented by two BCD digits. A novel design for single digit decimal multiplication that reduces the critical path delay and area is proposed in this research. Out of the possible 256 combinations for the 8-bit input, only hundred combinations are valid BCD inputs. In the hundred valid combinations only four combinations require 4 x 4 multiplication, combinations need x multiplication, and the remaining combinations use either x or x 3 multiplication. The proposed design makes use of this property. This design leads to more regular VLSI implementation, and does not require special registers for storing easy multiples. This is a fully parallel multiplier utilizing only combinational logic, and is extended to a Hex/Decimal multiplier that gives either a decimal output or a binary output. The accumulation ofpartial products generated using single digit multipliers is done by an array of multi-operand BCD adders for an (n-digit x n-digit) multiplication.

Fixed Point Decimal Multiplication Using RPS Algorithm

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. A novel design for single digit decimal multiplication that reduces the critical path delay and area for an iterative multiplier is proposed in this research. The partial products are generated using single digit multipliers, and are accumulated based on a novel RPS algorithm. This design uses n single digit multipliers for an n × n multiplication. The latency for the multiplication of two n-digit Binary Coded Decimal (BCD) operands is (n + 1) cycles and a new multiplication can begin every n cycle. The accumulation of final partial products and the first iteration of partial product generation for next set of inputs are done simultaneously. This iterative decimal multiplier offers low latency and high throughput, and can be extended for decimal floating-point multiplication.

On Szegö’s Type Theorems

This study is to look the effect of change in the ordering of the Fourier system on Szegö’s classical observations of asymptotic distribution of eigenvalues of finite Toeplitz forms.This is done by checking proofs and Szegö’s properties in the new set up.The Fourier system is unconditional [19], any arbitrary ordering of the Fourier system forms a basis for the Hilbert space L2 [-Π, Π].Here study about the classical Szegö’s theorem.Szegö’s type theorem for operators in L2(R+) and check its validity for certain multiplication operators.Since the trigonometric basis is not available in L2(R+) or in L2(R) .This study discussed about the classes of orderings of Haar System in L2 (R+) and in L2(R) in which Szegö’s Type TheoreT Am is valid for certain multiplication operators.It is divided into two sections. In the first section there is an ordering to Haar system in L2(R+) and prove that with respect to this ordering, Szegö’s Type theorem holds for general class of multiplication operators Tƒ with multiplier ƒ ε L2(R+), subject to some conditions on ƒ.Finally in second section more general classes of ordering of Haar system in L2(R+) and in L2(R) are identified in such a way that for certain classes of multiplication operators the asymptotic distribution of eigenvalues exists.

White Spot Syndrone Virus in Penaeids: Histopathology, Development of Polyclonal Antisera and a Cocktail Vaccine

The present study is the first comprehensive approach towards histopathology of White Spot Syndrome Virus (WSSV) in Penaeus indicus. WSSV could be demonstrated in the nuclei of all tissues, except those of midgut, subjected of electron microscopic observation. They were the nuclei of gill, foregut, heart, hepatopancreatic connective tissue, hindgut, nerve and dorsal aorta. A comparison was made between the electron microscopic and histopathological observations and a greater degree of correlation between the two in depicting the severity of the infection of the infection was unraveled. The study also illustrated variations in response and susceptibility of various tissues to WSSV infection. Accordingly, out of the tissues investigated, gill, foregut, hindgut and dorsal aorta exhibited advanced viral multiplication than the other tissues such as heart, midgut, nerve and hepatopancreas. Even though hepatocytes were not infected the connective tissue nuclei were packed with virions.

The photoemission optogalvanic effect in a Ne-Nd hollow cathode

Laser-induced photoelectric and photoemission optogalvanic effects in a Ne-Nd hollow cathode discharge have been studied using a continuous wave laser source. The potential barrier for photoinduced electron emission from the cathode decreases as the applied voltage is increased. Owing to secondary electron emission in the plasma, the photocurrent is greater than that without discharge. The multiplication of secondary electrons and the quantum efficiency are also investigated.

Design and synthesis of efficient mac architectures for high speed decimal processor

Most of the commercial and financial data are stored in decimal fonn. Recently, support for decimal arithmetic has received increased attention due to the growing importance in financial analysis, banking, tax calculation, currency conversion, insurance, telephone billing and accounting. Performing decimal arithmetic with systems that do not support decimal computations may give a result with representation error, conversion error, and/or rounding error. In this world of precision, such errors are no more tolerable. The errors can be eliminated and better accuracy can be achieved if decimal computations are done using Decimal Floating Point (DFP) units. But the floating-point arithmetic units in today's general-purpose microprocessors are based on the binary number system, and the decimal computations are done using binary arithmetic. Only few common decimal numbers can be exactly represented in Binary Floating Point (BF P). ln many; cases, the law requires that results generated from financial calculations performed on a computer should exactly match with manual calculations. Currently many applications involving fractional decimal data perform decimal computations either in software or with a combination of software and hardware. The performance can be dramatically improved by complete hardware DFP units and this leads to the design of processors that include DF P hardware.VLSI implementations using same modular building blocks can decrease system design and manufacturing cost. A multiplexer realization is a natural choice from the viewpoint of cost and speed.This thesis focuses on the design and synthesis of efficient decimal MAC (Multiply ACeumulate) architecture for high speed decimal processors based on IEEE Standard for Floating-point Arithmetic (IEEE 754-2008). The research goal is to design and synthesize deeimal'MAC architectures to achieve higher performance.Efficient design methods and architectures are developed for a high performance DFP MAC unit as part of this research.

Studies on genetic polymorphism in Santalum Album L.

Loss of natural sandal populations due to illicit felling, forest encroachment and spike disease have an adverse effect on genetic diversity of the species. To initiate any genetic improvement programme in sandal, a precise understanding of the population genetic diversity structure is essential. The concern over the loss of genetic variability in sandal is particularly critical, as there is hardly any information regarding the diversity status of the natural populations. Identifying fast growing, disease resistant, oil rich sandal trees through breeding and their mass multiplication for afforestation are the best method for ensuring sustainable supply of superior sandalwood. The healthy sandal trees existing in heavily spike diseased area can be used as a promising starting point for any such breeding programme (Venkatesh, 1978). So far, no genetic information is available regarding the resistant nature of spike disease evaded trees left in heavily infected patches. The high rate of depletion of the superior trees in South Indian sandal reserves due to illegal felling and spike disease has necessitated an urgent need for conservation of the surviving trees.Widespread occurrence of spike disease in Marayoor forest reserve was reported in 1981 (Ghosh and Balasundaran, 1995). Because of the high density of trees and varying intensity of spike disease, Marayoor sandal population was found to be ideal for experimental studies in sandal (Ghosh et al., 1985). Fifteen trees of reserve 51 of Marayoor range had been selected as candidate plus trees for growth and spike disease evasion . These trees have been selected for mass multiplication through tissue culture technique.

Polyphase Implementation of Non-recursive Comb Decimators for Sigma-Delta A/D Converters

In a sigma-delta analog to digital (A/D) As most of the sigma-delta ADC applications require converter, the most computationally intensive block is decimation filters with linear phase characteristics, the decimation filter and its hardware implementation symmetric Finite Impulse Response (FIR) filters are may require millions of transistors. Since these widely used for implementation. But the number of FIR converters are now targeted for a portable application, filter coefficients will be quite large for implementing a a hardware efficient design is an implicit requirement. narrow band decimation filter. Implementing decimation In this effect, this paper presents a computationally filter in several stages reduces the total number of filter efficient polyphase implementation of non-recursive coefficients, and hence reduces the hardware complexity cascaded integrator comb (CIC) decimators for and power consumption [2]. Sigma-Delta Converters (SDCs). The SDCs are The first stage of decimation filter can be operating at high oversampling frequencies and hence implemented very efficiently using a cascade of integrators require large sampling rate conversions. The filtering and comb filters which do not require multiplication or and rate reduction are performed in several stages to coefficient storage. The remaining filtering is performed reduce hardware complexity and power dissipation. either in single stage or in two stages with more complex The CIC filters are widely adopted as the first stage of FIR or infinite impulse response (IIR) filters according to decimation due to its multiplier free structure. In this the requirements. The amount of passband aliasing or research, the performance of polyphase structure is imaging error can be brought within prescribed bounds by compared with the CICs using recursive and increasing the number of stages in the CIC filter. The non-recursive algorithms in terms of power, speed and width of the passband and the frequency characteristics area. This polyphase implementation offers high speed outside the passband are severely limited. So, CIC filters operation and low power consumption. The polyphase are used to make the transition between high and low implementation of 4th order CIC filter with a sampling rates. Conventional filters operating at low decimation factor of '64' and input word length of sampling rate are used to attain the required transition '4-bits' offers about 70% and 37% of power saving bandwidth and stopband attenuation. compared to the corresponding recursive and Several papers are available in literature that deals non-recursive implementations respectively. The same with different implementations of decimation filter polyphase CIC filter can operate about 7 times faster architecture for sigma-delta ADCs. Hogenauer has than the recursive and about 3.7 times faster than the described the design procedures for decimation and non-recursive CIC filters.

Performance analysis of FIR digital filter design: RNS versus traditional

Residue Number System (RNS) based Finite Impulse Response (FIR) digital filters and traditional FIR filters. This research is motivated by the importance of an efficient filter implementation for digital signal processing. The comparison is done in terms of speed and area requirement for various filter specifications. RNS based FIR filters operate more than three times faster and consumes only about 60% of the area than traditional filter when number of filter taps is more than 32. The area for RNS filter is increasing at a lesser rate than that for traditional resulting in lower power consumption. RNS is a nonweighted number system without carry propogation between different residue digits.This enables simultaneous parallel processing on all the digits resulting in high speed addition and multiplication in the RNS domain

Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

High performance, low latency double digit decimal multiplier on ASIC and FPGA

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.

Pathological changes in Fenneropenaeus indicus experimentally infected with white spot virus and virus morphogenesis

To demonstrate pathological changes due to white spot virus infection in Fenneropenaeus indicus, a batch of hatchery bred quarantined animals was experimentally infected with the virus. Organs such as gills, foregut, mid-gut, hindgut, nerve, eye, heart, ovary and integument were examined by light and electron microscopy. Histopathological analyses revealed changes hitherto not reported in F. indicus such as lesions to the internal folding of gut resulted in syncytial mass sloughed off into lumen, thickening of hepatopancreatic connective tissue with vacuolization of tubules and necrosis of rectal pads in hindgut. Virus replication was seen in the crystalline tract region of the compound eye and eosinophilic granules infiltrated from its base. In the gill arch, dilation and disintegration of median blood vessel was observed. In the nervous tissues, encapsulation and subsequent atrophy of hypertrophied nuclei of the neurosecretory cells were found. Transmission electron microscopy showed viral replication and morphogenesis in cells of infected tissue. De novo formed vesicles covered the capsid forming a bilayered envelop opened at one end inside the virogenic stroma. Circular vesicles containing nuclear material was found fused with the envelop. Subsequent thickening of the envelop resulted in the fully formed virus. In this study, a correlation was observed between the stages of viral multiplication and the corresponding pathological changes in the cells during the WSV infection. Accordingly, gill and foregut tissues were found highly infected during the onset of clinical signs itself, and are proposed to be used as the tissues for routine disease diagnosis.