Expanding Concept of Sale the Taxation Dilemma

School of Legal Studies, Cochin University of Science & Technology

The power of taxation under the indian constitution

The Power Of Taxation Under The lndian Constitution, the subject of the present thesis has a wide ambit covering the entire federal field end deep constitutional significance traversing many of the principles like pith and substance, colourability, severebility etc. However, considerations of time, space and areas already investigated have indicated that the present study may be confined to the fundamental constitutional limitations end the federal problem. Thus the effect of fundamental rights, the commerce clause, immunity of instrumentalitis and the principle limiting the power of legislative delegation on the power of taxation has been studied. The distribution of taxes between the Union and units of the Indian federation leans so much over to the former and that part of this study has been directed to discover what devices can help the units to gain economic viability

Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

High performance, low latency double digit decimal multiplier on ASIC and FPGA

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.