Phenylethynylarene Based Donor-Acceptor Systems: Design, Synthesis and Photophysical Studies

This thesis Entitled phenylethynylarene based Donor-Acceptor systems:Desigh,Synthesis and Photophysical studies. A strategy for the design of donor-acceptor dyads, wherein decay of the charge separated (CS) state to low lying local triplet levels could possibly be prevented, is proposed. In order to examine this strategy, a linked donor-acceptor dyad BPEPPT with bis(phenylethYlly/)pyrene (BPEP) as the light absorber and acceptor and phenothiazine (PT) as donor was designed and photoinduced electron transfer in the dyad investigated. Absorption spectra of the dyad can be obtained by adding contributions due 10 the BPEP and PT moieties indicating that the constituents do not interact in the ground stale. Fluorescence of the BPEP moiety was efficiently quenched by the PT donor and this was attributed to electron lransfer from PT to BPEP. Picosecond transient absorption studies suggested formation of a charge separated state directly from the singlet excited state of BPEP. Nanosecond flash photolysis experiments gave long-ived transient absorptions assignable to PT radical cation and BPEP radical anion. These assignments were confirmed by oxygen quenching studies and secondary electron transfer experiments. Based on the available data, energy level diagram for BPEP-PT was constructed. The long lifetime of the charge separated state was attributed to the inverted region effects. The CS state did not undergo decay to low lying BPEP triplet indicating the success of our strategy

Nonparametric Estimation of Survivor Function in Bivariate Competing Risk Models’

So far, in the bivariate set up, the analysis of lifetime (failure time) data with multiple causes of failure is done by treating each cause of failure separately. with failures from other causes considered as independent censoring. This approach is unrealistic in many situations. For example, in the analysis of mortality data on married couples one would be interested to compare the hazards for the same cause of death as well as to check whether death due to one cause is more important for the partners’ risk of death from other causes. In reliability analysis. one often has systems with more than one component and many systems. subsystems and components have more than one cause of failure. Design of high-reliability systems generally requires that the individual system components have extremely high reliability even after long periods of time. Knowledge of the failure behaviour of a component can lead to savings in its cost of production and maintenance and. in some cases, to the preservation of human life. For the purpose of improving reliability. it is necessary to identify the cause of failure down to the component level. By treating each cause of failure separately with failures from other causes considered as independent censoring, the analysis of lifetime data would be incomplete. Motivated by this. we introduce a new approach for the analysis of bivariate competing risk data using the bivariate vector hazard rate of Johnson and Kotz (1975).

High performance, low latency double digit decimal multiplier on ASIC and FPGA

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.

Design and synthesis of efficient mac architectures for high speed decimal processor

Most of the commercial and financial data are stored in decimal fonn. Recently, support for decimal arithmetic has received increased attention due to the growing importance in financial analysis, banking, tax calculation, currency conversion, insurance, telephone billing and accounting. Performing decimal arithmetic with systems that do not support decimal computations may give a result with representation error, conversion error, and/or rounding error. In this world of precision, such errors are no more tolerable. The errors can be eliminated and better accuracy can be achieved if decimal computations are done using Decimal Floating Point (DFP) units. But the floating-point arithmetic units in today's general-purpose microprocessors are based on the binary number system, and the decimal computations are done using binary arithmetic. Only few common decimal numbers can be exactly represented in Binary Floating Point (BF P). ln many; cases, the law requires that results generated from financial calculations performed on a computer should exactly match with manual calculations. Currently many applications involving fractional decimal data perform decimal computations either in software or with a combination of software and hardware. The performance can be dramatically improved by complete hardware DFP units and this leads to the design of processors that include DF P hardware.VLSI implementations using same modular building blocks can decrease system design and manufacturing cost. A multiplexer realization is a natural choice from the viewpoint of cost and speed.This thesis focuses on the design and synthesis of efficient decimal MAC (Multiply ACeumulate) architecture for high speed decimal processors based on IEEE Standard for Floating-point Arithmetic (IEEE 754-2008). The research goal is to design and synthesize deeimal'MAC architectures to achieve higher performance.Efficient design methods and architectures are developed for a high performance DFP MAC unit as part of this research.