Acoustic Structure Interaction For Floating Structure Under Moving Load

The present thesis concentrates largely on sound radiation from floating structure due to moving load

Design and synthesis of efficient mac architectures for high speed decimal processor

Most of the commercial and financial data are stored in decimal fonn. Recently, support for decimal arithmetic has received increased attention due to the growing importance in financial analysis, banking, tax calculation, currency conversion, insurance, telephone billing and accounting. Performing decimal arithmetic with systems that do not support decimal computations may give a result with representation error, conversion error, and/or rounding error. In this world of precision, such errors are no more tolerable. The errors can be eliminated and better accuracy can be achieved if decimal computations are done using Decimal Floating Point (DFP) units. But the floating-point arithmetic units in today's general-purpose microprocessors are based on the binary number system, and the decimal computations are done using binary arithmetic. Only few common decimal numbers can be exactly represented in Binary Floating Point (BF P). ln many; cases, the law requires that results generated from financial calculations performed on a computer should exactly match with manual calculations. Currently many applications involving fractional decimal data perform decimal computations either in software or with a combination of software and hardware. The performance can be dramatically improved by complete hardware DFP units and this leads to the design of processors that include DF P hardware.VLSI implementations using same modular building blocks can decrease system design and manufacturing cost. A multiplexer realization is a natural choice from the viewpoint of cost and speed.This thesis focuses on the design and synthesis of efficient decimal MAC (Multiply ACeumulate) architecture for high speed decimal processors based on IEEE Standard for Floating-point Arithmetic (IEEE 754-2008). The research goal is to design and synthesize deeimal'MAC architectures to achieve higher performance.Efficient design methods and architectures are developed for a high performance DFP MAC unit as part of this research.

An investigation on the preparation and properties of some transparent conducting oxides and lead selenide thin films”

The investigation of physical properties of matter has progressed so much during the last hundred years. Today physics is divided in to a large distinct group of special branches. These branches are distinguished by the particular area studied, method of investigation and so on. An independent and important branch that has developed is the physics ofthin films.Any object in solid or liquid form with one of its dimensions very much smaller than that of the other two may be called a thin film. It is having only one common property, namely, one of their dimensions is very small, though all their physical properties may be different. Thin layers of oil, floating on the surface of water, with their fascinating colours, have attracted men’s curiosity from time immemorial. The earliest application of thin films was the protective coatings in the form of paints. A thin layer of tin has been used from ancient times to protect copper utensils from corrosion. Indium thin films are used in certain applications on account of their good lubricating property. Relay contacts are coated with thin films of rare earth metals in order to prevent burning due to arcing. Hard coatings are also available using diamond like carbon (i-carbon). The basic properties of thin films are of considerable interest because of their potential applications in various fields of science and technology

Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

High performance, low latency double digit decimal multiplier on ASIC and FPGA

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.

Fixed Point Decimal Multiplication Using RPS Algorithm

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. A novel design for single digit decimal multiplication that reduces the critical path delay and area for an iterative multiplier is proposed in this research. The partial products are generated using single digit multipliers, and are accumulated based on a novel RPS algorithm. This design uses n single digit multipliers for an n × n multiplication. The latency for the multiplication of two n-digit Binary Coded Decimal (BCD) operands is (n + 1) cycles and a new multiplication can begin every n cycle. The accumulation of final partial products and the first iteration of partial product generation for next set of inputs are done simultaneously. This iterative decimal multiplier offers low latency and high throughput, and can be extended for decimal floating-point multiplication.

Utilization of aquatic macrophyte Spirodela polyrhiza as phytotoxicological assessment and phytoremediation tool in selected polluted wetland sites in Ernakulam district

One of the objectives of the current investigation was to evaluate the effectiveness of Spirodela polyrhiza to remove heavy metals and other contaminants from the water samples collected from wetland sites of Eloor and Kannamaly under controlled conditions .The results obtained from the current study suggest that the test material S. polyrrhiza should be used in the biomonitoring and phytoremediation of municipal, agricultural and industrial effluents because of their simplicity, sensitivity and cost-effectiveness. The study throws light on the potential of this plant which can be used as an assessment tool in two diverse wetland in Ernakulum district. The results show the usefulness of combining physicochemical analysis with bioassays as such approach ensures better understanding of the toxicity of chemical pollutants and their influence on plant health. The results shows the suitability of Spirodela plant for surface water quality assessment as all selected parameters showed consistency with respect to water samples collected over a 3-monitoring periods. Similarly the relationship between the change in exposure period (2, 4 and 8 days) with the parameters were also studied in detail. Spirodela are consistent test material as they are homogeneous plant material; due to predominantly vegetative reproduction. New fronds are formed by clonal propagation thus, producing a population of genetically homogeneous plants. The result is small variability between treated individuals. It has been observed that phytoremediation of water samples collected from Eloor and Kannamaly using the floating plant system is a predominant method which is economic to construct, requires little maintenance and eco friendly.