Barriers Faced By Micro, Small And Medium Enterprises In Raising Finance

Worldwide, Micro, Small and Medium Enterprises (MSMEs) have been accepted as an engine of economic growth and for promoting equitable development. In developing countries including India, Micro, Small and Medium Enterprises sector constitute an important part in its development. In spite of this importance, this sector face number of constraints like absence of adequate and timely supply of bank finance, difficulties in procuring raw materials, marketing and distribution challenges and non availability of suitable technology. Review of literature found that there exists problem in accessing finance from banks and financial institutions and this problem may differ from region to region, between sectors, or between individual enterprises within a sector. This paper tries to identify the various barriers faced by these units in raising finance and also try to identify the various sources of finance other than banks. The study is based upon the primary data collected from the 200 MSMEs owners in Kozhikode District of Kerala. The data has been analysed with the help of percentage. The study attempts to submit some recommendations to enhance the overall credit accessibility to MSMEs sector

Design and synthesis of efficient mac architectures for high speed decimal processor

Most of the commercial and financial data are stored in decimal fonn. Recently, support for decimal arithmetic has received increased attention due to the growing importance in financial analysis, banking, tax calculation, currency conversion, insurance, telephone billing and accounting. Performing decimal arithmetic with systems that do not support decimal computations may give a result with representation error, conversion error, and/or rounding error. In this world of precision, such errors are no more tolerable. The errors can be eliminated and better accuracy can be achieved if decimal computations are done using Decimal Floating Point (DFP) units. But the floating-point arithmetic units in today's general-purpose microprocessors are based on the binary number system, and the decimal computations are done using binary arithmetic. Only few common decimal numbers can be exactly represented in Binary Floating Point (BF P). ln many; cases, the law requires that results generated from financial calculations performed on a computer should exactly match with manual calculations. Currently many applications involving fractional decimal data perform decimal computations either in software or with a combination of software and hardware. The performance can be dramatically improved by complete hardware DFP units and this leads to the design of processors that include DF P hardware.VLSI implementations using same modular building blocks can decrease system design and manufacturing cost. A multiplexer realization is a natural choice from the viewpoint of cost and speed.This thesis focuses on the design and synthesis of efficient decimal MAC (Multiply ACeumulate) architecture for high speed decimal processors based on IEEE Standard for Floating-point Arithmetic (IEEE 754-2008). The research goal is to design and synthesize deeimal'MAC architectures to achieve higher performance.Efficient design methods and architectures are developed for a high performance DFP MAC unit as part of this research.