Studies on underwater propagation development of programmable arrays

The thesis presented here includes the designing of underwater transducer arrays, taking into account the ‘interaction effects’ [30] among the closely packed radiators. Methods of minimizing the ‘interaction effects‘ by modifying the radiating aperture, are investigated. The need for this study arises as it is one of the important peculiar limitations that stands in the way of achieving maximum range of transmission of acoustic signals. Application of the modified array format for the generation of narrow beam low frequency sound waves, through nonlinear interactions, is discussed. Other techniques that can be advantageously exploited in array synthesis are also investigated

Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard