4 resultados para Dielectric layer

em Cochin University of Science


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Usage of a dielectric multilayer around a dielectric Sample is studied as a means for improving the efficiency in multimode microwave- heating cavities. The results show that by using additional dielectric constant layers the appearance of undesired reflections at the sample-air interface is avoided and higher power -absorption rates within the sample and high -efficiency designs are obtained

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AC thin film electroluminescent devices of MIS and MISIM have been fabricated with a novel dielectric layer of Eu2O3 as an insulator. The threshold voltage for light emission is found to depend strongly on the frequency of excitation source in these devices. These devices are fabricated with an active layer of ZnS:Mn and a novel dielectric layer of Eu2O3 as an insulator. The observed frequency dependence of brightness-voltage characteristics has been explained on the basis of the loss characteristic of the insulator layer. Changes in the threshold voltage and brightness with variation in emitting or insulating film thickness have been investigated in metal-insulator-semiconductor (MIS) structures. It has been found that the decrease in brightness occurring with decreasing ZnS layer thickness can be compensated by an increase in brightness obtained by reducing the insulator thickness. The optimal condition for low threshold voltage and higher stability has been shown to occur when the active layer to insulator thickness ratio lies between one and two.

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Present work deals with the Preparation and characterization of high-k aluminum oxide thin films by atomic layer deposition for gate dielectric applications.The ever-increasing demand for functionality and speed for semiconductor applications requires enhanced performance, which is achieved by the continuous miniaturization of CMOS dimensions. Because of this miniaturization, several parameters, such as the dielectric thickness, come within reach of their physical limit. As the required oxide thickness approaches the sub- l nm range, SiO 2 become unsuitable as a gate dielectric because its limited physical thickness results in excessive leakage current through the gate stack, affecting the long-term reliability of the device. This leakage issue is solved in the 45 mn technology node by the integration of high-k based gate dielectrics, as their higher k-value allows a physically thicker layer while targeting the same capacitance and Equivalent Oxide Thickness (EOT). Moreover, Intel announced that Atomic Layer Deposition (ALD) would be applied to grow these materials on the Si substrate. ALD is based on the sequential use of self-limiting surface reactions of a metallic and oxidizing precursor. This self-limiting feature allows control of material growth and properties at the atomic level, which makes ALD well-suited for the deposition of highly uniform and conformal layers in CMOS devices, even if these have challenging 3D topologies with high aspect-ratios. ALD has currently acquired the status of state-of-the-art and most preferred deposition technique, for producing nano layers of various materials of technological importance. This technique can be adapted to different situations where precision in thickness and perfection in structures are required, especially in the microelectronic scenario.

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Nanosized ZnFe2O4 particles containing traces of a-Fe2O3 by intent were produced by low temperature chemical coprecipitation methods. These particles were subjected to high-energy ball milling. These were then characterised using X-ray diffraction, magnetisation and dielectric studies. The effect of milling on zinc ferrite particles have been studied with a view to ascertaining the anomalous behaviour of these materials in the nanoregime. X-ray diffraction and magnetisation studies carried out show that these particles are associated with strains and it is the surface effects that contribute to the magnetisation. Hematite percentage, probably due to decomposition of zinc ferrite, increases with milling. Dielectric behaviour of these particles is due to interfacial polarisation as proposed by Koops. Also the defects caused by the milling produce traps in the surface layer contributes to dielectric permittivity via spin polarised electron tunnelling between grains. The ionic mechanism is enhanced in dielectrics with the rise in temperature which results in the increase of dielectric permittivity with temperature.