Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

High performance, low latency double digit decimal multiplier on ASIC and FPGA

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.

Fabrication of a quantum well heterostructure based on plasma polymerized aniline and its characterization using STM/STS

Two-dimensional electronic systems play a crucial role in modern electronics and offer a multitude of opportunities to study the fundamental phenomena at low dimensional physics. A quantum well heterostructure based on polyaniline (P) and iodine doped polyaniline (I) thin films were fabricated using radio frequency plasma polymerization on indium tin oxide coated glass plate. Scanning probe microscopy and scanning electron microscopy studies were employed to study the morphology and roughness of the polymer thin films. Local electronic density of states (LDOS) of the P–I–P heterostructures is probed using scanning tunnelling spectroscopy (STS). A step like LDOS is observed in the P–I–P heterostructure and is attributed to the quantum well confinement of electrons in the polymer heterostructure.