Nonlinear Dynamics of Nd:YAG lasers: Hopf bifurcation, Multistability and Chaotic Synchronization

In this thesis we have presented some aspects of the nonlinear dynamics of Nd:YAG lasers including synchronization, Hopf bifurcation, chaos control and delay induced multistability.We have chosen diode pumped Nd:YAG laser with intracavity KTP crystal operating with two mode and three mode output as our model system.Different types of orientation for the laser cavity modes were considered to carry out the studies. For laser operating with two mode output we have chosen the modes as having parallel polarization and perpendicular polarization. For laser having three mode output, we have chosen them as two modes polarized parallel to each other while the third mode polarized orthogonal to them.

Electrical switching studies on the thin films of polyfuran and polyacrylonitrile prepared by plasma polymerisation and vacuum evaporated amorphous silicon

This thesis Entitled Electrical switching studies on the thin flims of polyfuran and polyacrylonitrile prepared by plasma polymerisation and vacuum evaporated amorphous silicon.A general introduction to the switching and allied phenomena is presented. Subsequently, developments of switching in thin films are described. The Mott transition is qualitatively presented. The working of a switching transitor is outlined and compared to the switching observed in thin films. Characteristic parameters of switching such as threshold voltage, time response to a, voltage pulse, and delay time are described. The various switching configurations commonly used are discussed. The mechanisms used to explain the switching behaviour like thermal, electrothermal and purely electronic are reviewed. Finally the scope, feasibility and the importance of polymer thin films in switching are highlighted.

Criminal justice system in pondicherry - a comparative critical study of the past and the presen

The Union Territory of Pondicherry prior to its merger with the Indian Union was a French Colony. The erstwhile territory of Pondicherry along with its hamlets, namely, KARAIKKAL, MAHE and YANAM was administered by the French Regime. Before it was established by French in 1 6 74 A.D. it was part of Vijayanagara Empire. Prior to this, Pondicherry was a part of the Kingdom of Chola and Pallava Kings. During French Regime, the laws which were in force in France in relation to administration of civil and criminal justice were extended to the erstwhile Territory of Pondicherry. Thus while Pondicherry stood influenced by the Inquisitorial system since the beginning of the 18th century, the neighboring states forming part of the Indian Union since Independence came under the Influence of the British system, viz. accusatorial system. The territory of Pondicherry, for administrative reasons, came to be merged with the Indian Union in the early 60's. Following the merger, the Indian administration sought to extent its own laws from time to time replacing erstwhile French Laws, however, subject to certain savings. Thus the transitional period witnessed consequential changes in the administration of the territory, including the sphere of judicial system. Since I 963, the Union Territory of Pondicherry was brought under the spell of the Indian Legal System The people in Pondicherry ' thus have had the benefit of experiencing both the svstems. Their experiences will be of much help to those who undertake comparative studies in law. The plus and minus points of the respective systems help one to develop a detachment that helps independent evaluation of the svstents. The result of these studies could be relevant in revitalising our criminal systems.The present system is evaluated in the light of the past system. New dimensions are added by way' of an empirical study also.

High performance, low latency double digit decimal multiplier on ASIC and FPGA

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.

Classification of Mammograms and DW T based Detection of Microcalcification

Cancer treatment is most effective when it is detected early and the progress in treatment will be closely related to the ability to reduce the proportion of misses in the cancer detection task. The effectiveness of algorithms for detecting cancers can be greatly increased if these algorithms work synergistically with those for characterizing normal mammograms. This research work combines computerized image analysis techniques and neural networks to separate out some fraction of the normal mammograms with extremely high reliability, based on normal tissue identification and removal. The presence of clustered microcalcifications is one of the most important and sometimes the only sign of cancer on a mammogram. 60% to 70% of non-palpable breast carcinoma demonstrates microcalcifications on mammograms [44], [45], [46].WT based techniques are applied on the remaining mammograms, those are obviously abnormal, to detect possible microcalcifications. The goal of this work is to improve the detection performance and throughput of screening-mammography, thus providing a ‘second opinion ‘ to the radiologists. The state-of- the- art DWT computation algorithms are not suitable for practical applications with memory and delay constraints, as it is not a block transfonn. Hence in this work, the development of a Block DWT (BDWT) computational structure having low processing memory requirement has also been taken up.

Pulse Wave Propagating in Coplanar Waveguides (cPWS) on LTCC Substrates

The propagation of pulse waves in coplanar waveguides (CPWs) is investigated, and these CPWs are assumed to be fabricated on a single -layer low- temperature co-fired ceramic (LTCC) substrate. The input pulse wave can be a Gaussian pulse or a sinusoldally modulated Gaussian pulse. Based on the standard Galerkin 's method in the spectral domain, combined with fast Fourier transform (FFT), the pulse waveform and delay in CPWs are demonstrated and compared for a second plate, oriented orthogonally to the primary planar element, thus producing a crossed planar monopole (CPM), which is simpler to produce and has lower cost than a conical monopole. In this paper, further measurements have been made on this element

Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

A location aided cooperative caching protocol for mobile ad hoc networks

Cooperative caching is an attractive solution for reducing bandwidth demands and network latency in mobile ad hoc networks. Deploying caches in mobile nodes can reduce the overall traffic considerably. Cache hits eliminate the need to contact the data source frequently, which avoids additional network overhead. In this paper we propose a data discovery and cache management policy for cooperative caching, which reduces the caching overhead and delay by reducing the number of control messages flooded in to the network. A cache discovery process based on location of neighboring nodes is developed for this. The cache replacement policy we propose aims at increasing the cache hit ratio. The simulation results gives a promising result based on the metrics of studies

Energy Efficient Cache Discovery in Wireless Mobile Ad oc Networks

Data caching is an attractive solution for reducing bandwidth demands and network latency in mobile ad hoc networks. Deploying caches in mobile nodes can reduce the overall traf c considerably. Cache hits eliminate the need to contact the data source frequently, which avoids additional network overhead. In this paper we propose a data discovery and cache management policy for cooperative caching, which reduces the power usage, caching overhead and delay by reducing the number of control messages flooded into the network .A cache discovery process based on position cordinates of neighboring nodes is developed for this .The stimulstion results gives a promising result based on the metrics of the studies.

Performance of Supply Chain when using selected Coordination Mechanisms

Coordination among supply chain members is essential for better supply chain performance. An effective method to improve supply chain coordination is to implement proper coordination mechanisms. The primary objective of this research is to study the performance of a multi-level supply chain while using selected coordination mechanisms separately, and in combination, under lost sale and back order cases. The coordination mechanisms used in this study are price discount, delay in payment and different types of information sharing. Mathematical modelling and simulation modelling are used in this study to analyse the performance of the supply chain using these mechanisms. Initially, a three level supply chain consisting of a supplier, a manufacturer and a retailer has been used to study the combined effect of price discount and delay in payment on the performance (profit) of supply chain using mathematical modelling. This study showed that implementation of individual mechanisms improves the performance of the supply chain compared to ‘no coordination’. When more than one mechanism is used in combination, performance in most cases further improved. The three level supply chain considered in mathematical modelling was then extended to a three level network supply chain consisting of a four retailers, two wholesalers, and a manufacturer with an infinite part supplier. The performance of this network supply chain was analysed under both lost sale and backorder cases using simulation modelling with the same mechanisms: ‘price discount and delay in payment’ used in mathematical modelling. This study also showed that the performance of the supply chain is significantly improved while using combination of mechanisms as obtained earlier. In this study, it is found that the effect (increase in profit) of ‘delay in payment’ and combination of ‘price discount’ & ‘delay in payment’ on SC profit is relatively high in the case of lost sale. Sensitivity analysis showed that order cost of the retailer plays a major role in the performance of the supply chain as it decides the order quantity of the other players in the supply chain in this study. Sensitivity analysis also showed that there is a proportional change in supply chain profit with change in rate of return of any player. In the case of price discount, elasticity of demand is an important factor to improve the performance of the supply chain. It is also found that the change in permissible delay in payment given by the seller to the buyer affects the SC profit more than the delay in payment availed by the buyer from the seller. In continuation of the above, a study on the performance of a four level supply chain consisting of a manufacturer, a wholesaler, a distributor and a retailer with ‘information sharing’ as coordination mechanism, under lost sale and backorder cases, using a simulation game with live players has been conducted. In this study, best performance is obtained in the case of sharing ‘demand and supply chain performance’ compared to other seven types of information sharing including traditional method. This study also revealed that effect of information sharing on supply chain performance is relatively high in the case of lost sale than backorder. The in depth analysis in this part of the study showed that lack of information sharing need not always be resulting in bullwhip effect. Instead of bullwhip effect, lack of information sharing produced a huge hike in lost sales cost or backorder cost in this study which is also not favorable for the supply chain. Overall analysis provided the extent of improvement in supply chain performance under different cases. Sensitivity analysis revealed useful insights about the decision variables of supply chain and it will be useful for the supply chain management practitioners to take appropriate decisions.

Analysis and Design of an Adaptive Polynomial Predistorter with the Loop Delay Estimator

Most adaptive linearization circuits for the nonlinear amplifier have a feedback loop that returns the output signal oj'tne eunplifier to the lineurizer. The loop delay of the linearizer most be controlled precisely so that the convergence of the linearizer should be assured lot this Letter a delay control circuit is presented. It is a delay lock loop (ULL) with it modified early-lute gate and can he easily applied to a DSP implementation. The proposed DLL circuit is applied to an adaptive linearizer with the use of a polynomial predistorter, and the simulalion for a 16-QAM signal is performed. The simulation results show that the proposed DLL eliminates the delay between the reference input signal and the delayed feedback signal of the linearizing circuit perfectly, so that the predistorter polynomial coefficients converge into the optimum value and a high degree of linearization is achieved