Loss characterization in rhodamine 6G doped polymer film waveguide by side illumination fluorescence

We report the position dependent tuning of fluorescence emission from rhodamine 6G doped polymethylmethacrylate film waveguide using a side illumination technique. The transmitted fluorescence as a function of the distance from the point of illumination is measured by translating the waveguide horizontally across a monochromatic light source. This technique has been utilized to characterize the optical loss in dye doped waveguides. We observe that the optical loss coefficients for shorter and longer distances of propagation through the dye doped waveguide are different. At longer distance of propagation a decrease in optical loss coefficient is observed

Characterization of rhodamine 6G doped polymer optical fiber by side illumination fluorescence

The length-dependent tuning of the fluorescence spectra of a dye doped polymer fiber is reported. The fiber is pumped sideways and the fluorescence is measured from one of the ends. The excitation of a finite length of dye doped fiber is done by a diode pumped solid state laser at a wavelength of 532 nm. The fluorescence emission is measured at various positions of the fiber starting from a position closer to the pumping region and then progressing toward the other end of the fiber. We observe that the optical loss coefficients for shorter and longer distances of propagation through the dye doped fiber are different. At longer distances of propagation, a decrease in optical loss coefficient is observed. The fluorescence peaks exhibit a redshift of 12 nm from 589 to 610 nm as the point of illumination progresses toward the detector end. This is attributed to the self-absorption and re-emission of the laser dye in the fiber.

Side illumination fluorescence emission characteristics from a dye doped polymer optical fiber under two-photon excitation.

Two-photon excited (TPE) side illumination fluorescence studies in a Rh6G-RhB dye mixture doped polymer optical fiber (POF) and the effect of energy transfer on the attenuation coefficient is reported. The dye doped POF is pumped sideways using 800 nm, 70 fs laser pulses from a Ti:sapphire laser, and the TPE fluorescence emission is collected from the end of the fiber for different propagation distances. The fluorescence intensity of RhB doped POF is enhanced in the presence of Rh6G as a result of energy transfer from Rh6G to RhB. Because of the reabsorption and reemission process in dye molecules, an effective energy transfer is observed from the shorter wavelength part of the fluorescence spectrum to the longer wavelength part as the propagation distance is increased in dye doped POF. An energy transfer coefficient is found to be higher at shorter propagation distances compared to longer distances. A TPE fluorescence signal is used to characterize the optical attenuation coefficient in dye doped POF. The attenuation coefficient decreases at longer propagation distances due to the reabsorption and reemission process taking place within the dye doped fiber as the propagation distance is increased.

Indian Mathematics Related to Architecture and Other Areas With Special Reference to Kerala

Department of Mathematics, Cochin University of Science and Technology

An Error-Localization, Validation and Optimization Tool for Embedded Code Augmentation: an Architecture Oriented Approach

Embedded systems are usually designed for a single or a specified set of tasks. This specificity means the system design as well as its hardware/software development can be highly optimized. Embedded software must meet the requirements such as high reliability operation on resource-constrained platforms, real time constraints and rapid development. This necessitates the adoption of static machine codes analysis tools running on a host machine for the validation and optimization of embedded system codes, which can help meet all of these goals. This could significantly augment the software quality and is still a challenging field.Embedded systems are usually designed for a single or a specified set of tasks. This specificity means the system design as well as its hardware/software development can be highly optimized. Embedded software must meet the requirements such as high reliability operation on resource-constrained platforms, real time constraints and rapid development. This necessitates the adoption of static machine codes analysis tools running on a host machine for the validation and optimization of embedded system codes, which can help meet all of these goals. This could significantly augment the software quality and is still a challenging field.Embedded systems are usually designed for a single or a specified set of tasks. This specificity means the system design as well as its hardware/software development can be highly optimized. Embedded software must meet the requirements such as high reliability operation on resource-constrained platforms, real time constraints and rapid development. This necessitates the adoption of static machine codes analysis tools running on a host machine for the validation and optimization of embedded system codes, which can help meet all of these goals. This could significantly augment the software quality and is still a challenging field.Embedded systems are usually designed for a single or a specified set of tasks. This specificity means the system design as well as its hardware/software development can be highly optimized. Embedded software must meet the requirements such as high reliability operation on resource-constrained platforms, real time constraints and rapid development. This necessitates the adoption of static machine codes analysis tools running on a host machine for the validation and optimization of embedded system codes, which can help meet all of these goals. This could significantly augment the software quality and is still a challenging field.This dissertation contributes to an architecture oriented code validation, error localization and optimization technique assisting the embedded system designer in software debugging, to make it more effective at early detection of software bugs that are otherwise hard to detect, using the static analysis of machine codes. The focus of this work is to develop methods that automatically localize faults as well as optimize the code and thus improve the debugging process as well as quality of the code.Validation is done with the help of rules of inferences formulated for the target processor. The rules govern the occurrence of illegitimate/out of place instructions and code sequences for executing the computational and integrated peripheral functions. The stipulated rules are encoded in propositional logic formulae and their compliance is tested individually in all possible execution paths of the application programs. An incorrect sequence of machine code pattern is identified using slicing techniques on the control flow graph generated from the machine code.An algorithm to assist the compiler to eliminate the redundant bank switching codes and decide on optimum data allocation to banked memory resulting in minimum number of bank switching codes in embedded system software is proposed. A relation matrix and a state transition diagram formed for the active memory bank state transition corresponding to each bank selection instruction is used for the detection of redundant codes. Instances of code redundancy based on the stipulated rules for the target processor are identified.This validation and optimization tool can be integrated to the system development environment. It is a novel approach independent of compiler/assembler, applicable to a wide range of processors once appropriate rules are formulated. Program states are identified mainly with machine code pattern, which drastically reduces the state space creation contributing to an improved state-of-the-art model checking. Though the technique described is general, the implementation is architecture oriented, and hence the feasibility study is conducted on PIC16F87X microcontrollers. The proposed tool will be very useful in steering novices towards correct use of difficult microcontroller features in developing embedded systems.

Face Recognition using Probabilistic Neural Networks

In this paper we address the problem of face detection and recognition of grey scale frontal view images. We propose a face recognition system based on probabilistic neural networks (PNN) architecture. The system is implemented using voronoi/ delaunay tessellations and template matching. Images are segmented successfully into homogeneous regions by virtue of voronoi diagram properties. Face verification is achieved using matching scores computed by correlating edge gradients of reference images. The advantage of classification using PNN models is its short training time. The correlation based template matching guarantees good classification results

A Generic Software Architecture for a Domain Specific Distributed Embedded System

In this paper, we have evolved a generic software architecture for a domain specific distributed embedded system. The system under consideration belongs to the Command, Control and Communication systems domain. The systems in such domain have very long operational lifetime. The quality attributes of these systems are equally important as the functional requirements. The main guiding principle followed in this paper for evolving the software architecture has been functional independence of the modules. The quality attributes considered most important for the system are maintainability and modifiability. Architectural styles best suited for the functionally independent modules are proposed with focus on these quality attributes. The software architecture for the system is envisioned as a collection of architecture styles of the functionally independent modules identified

Face Recognition using Probabilistic Neural Networks

n this paper we address the problem of face detection and recognition of grey scale frontal view images. We propose a face recognition system based on probabilistic neural networks (PNN) architecture. The system is implemented using voronoi/ delaunay tessellations and template matching. Images are segmented successfully into homogeneous regions by virtue of voronoi diagram properties. Face verification is achieved using matching scores computed by correlating edge gradients of reference images. The advantage of classification using PNN models is its short training time. The correlation based template matching guarantees good classification results.

A Hybrid Architecture for Recognising Speech Signals in Malayalam

Speech is the primary, most prominent and convenient means of communication in audible language. Through speech, people can express their thoughts, feelings or perceptions by the articulation of words. Human speech is a complex signal which is non stationary in nature. It consists of immensely rich information about the words spoken, accent, attitude of the speaker, expression, intention, sex, emotion as well as style. The main objective of Automatic Speech Recognition (ASR) is to identify whatever people speak by means of computer algorithms. This enables people to communicate with a computer in a natural spoken language. Automatic recognition of speech by machines has been one of the most exciting, significant and challenging areas of research in the field of signal processing over the past five to six decades. Despite the developments and intensive research done in this area, the performance of ASR is still lower than that of speech recognition by humans and is yet to achieve a completely reliable performance level. The main objective of this thesis is to develop an efficient speech recognition system for recognising speaker independent isolated words in Malayalam.