Existence of multiple attractors and the nature of bifurcations in a discontinuous logistic map

We present the analytical investigations on a logistic map with a discontinuity at the centre. An explanation for the bifurcation phenomenon in discontinuous systems is presented. We establish that whenever the elements of an n-cycle (n > 1) approach the discontinuities of the nth iterate of the map, a bifurcation other than the usual period-doubling one takes place. The periods of the cycles decrease in an arithmetic progression, as the control parameter is varied. The system also shows the presence of multiple attractors. Our results are verified by numerical experiments as well.

Complexity quantification of dense array EEG using sample entropy analysis

n this paper, a time series complexity analysis of dense array electroencephalogram signals is carried out using the recently introduced Sample Entropy (SampEn) measure. This statistic quantifies the regularity in signals recorded from systems that can vary from the purely deterministic to purely stochastic realm. The present analysis is conducted with an objective of gaining insight into complexity variations related to changing brain dynamics for EEG recorded from the three cases of passive, eyes closed condition, a mental arithmetic task and the same mental task carried out after a physical exertion task. It is observed that the statistic is a robust quantifier of complexity suited for short physiological signals such as the EEG and it points to the specific brain regions that exhibit lowered complexity during the mental task state as compared to a passive, relaxed state. In the case of mental tasks carried out before and after the performance of a physical exercise, the statistic can detect the variations brought in by the intermediate fatigue inducing exercise period. This enhances its utility in detecting subtle changes in the brain state that can find wider scope for applications in EEG based brain studies.

Design and synthesis of efficient mac architectures for high speed decimal processor

Most of the commercial and financial data are stored in decimal fonn. Recently, support for decimal arithmetic has received increased attention due to the growing importance in financial analysis, banking, tax calculation, currency conversion, insurance, telephone billing and accounting. Performing decimal arithmetic with systems that do not support decimal computations may give a result with representation error, conversion error, and/or rounding error. In this world of precision, such errors are no more tolerable. The errors can be eliminated and better accuracy can be achieved if decimal computations are done using Decimal Floating Point (DFP) units. But the floating-point arithmetic units in today's general-purpose microprocessors are based on the binary number system, and the decimal computations are done using binary arithmetic. Only few common decimal numbers can be exactly represented in Binary Floating Point (BF P). ln many; cases, the law requires that results generated from financial calculations performed on a computer should exactly match with manual calculations. Currently many applications involving fractional decimal data perform decimal computations either in software or with a combination of software and hardware. The performance can be dramatically improved by complete hardware DFP units and this leads to the design of processors that include DF P hardware.VLSI implementations using same modular building blocks can decrease system design and manufacturing cost. A multiplexer realization is a natural choice from the viewpoint of cost and speed.This thesis focuses on the design and synthesis of efficient decimal MAC (Multiply ACeumulate) architecture for high speed decimal processors based on IEEE Standard for Floating-point Arithmetic (IEEE 754-2008). The research goal is to design and synthesize deeimal'MAC architectures to achieve higher performance.Efficient design methods and architectures are developed for a high performance DFP MAC unit as part of this research.

On infinite graphs and related matrices

This thesis Entitled On Infinite graphs and related matrices.ln the last two decades (iraph theory has captured wide attraction as a Mathematical model for any system involving a binary relation. The theory is intimately related to many other branches of Mathematics including Matrix Theory Group theory. Probability. Topology and Combinatorics . and has applications in many other disciplines..Any sort of study on infinite graphs naturally involves an attempt to extend the well known results on the much familiar finite graphs. A graph is completely determined by either its adjacencies or its incidences. A matrix can convey this information completely. This makes a proper labelling of the vertices. edges and any other elements considered, an inevitable process. Many types of labelling of finite graphs as Cordial labelling, Egyptian labelling, Arithmetic labeling and Magical labelling are available in the literature. The number of matrices associated with a finite graph are too many For a study ofthis type to be exhaustive. A large number of theorems have been established by various authors for finite matrices. The extension of these results to infinite matrices associated with infinite graphs is neither obvious nor always possible due to convergence problems. In this thesis our attempt is to obtain theorems of a similar nature on infinite graphs and infinite matrices. We consider the three most commonly used matrices or operators, namely, the adjacency matrix

A study on fuzzy semi inner product spaces

Mathematical models are often used to describe physical realities. However, the physical realities are imprecise while the mathematical concepts are required to be precise and perfect. The 1st chapter give a brief summary of the arithmetic of fuzzy real numbers and the fuzzy normed algebra M(I). Also we explain a few preliminary definitions and results required in the later chapters. Fuzzy real numbers are introduced by Hutton,B [HU] and Rodabaugh, S.E[ROD]. Our definition slightly differs from this with an additional minor restriction. The definition of Clementina Felbin [CL1] is entirely different. The notations of [HU]and [M;Y] are retained inspite of the slight difference in the concept.the 3rd chapter In this chapter using the completion M'(I) of M(I) we give a fuzzy extension of real Hahn-Banch theorem. Some consequences of this extension are obtained. The idea of real fuzzy linear functional on fuzzy normed linear space is introduced. Some of its properties are studied. In the complex case we get only a slightly weaker analogue for the Hahn-Banch theorem, than the one [B;N] in the crisp case

A new look at reversible logic implementation of decimal adder

Reversibility plays a fundamental role when logic gates such as AND, OR, and XOR are not reversible. computations with minimal energy dissipation are considered. Hence, these gates dissipate heat and may reduce the life of In recent years, reversible logic has emerged as one of the most the circuit. So, reversible logic is in demand in power aware important approaches for power optimization with its circuits. application in low power CMOS, quantum computing and A reversible conventional BCD adder was proposed in using conventional reversible gates.

Quick Addition of Decimals Using Reversible Conservative Logic

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, nanotechnology and quantum computing. This research proposes quick addition of decimals (QAD) suitable for multi-digit BCD addition, using reversible conservative logic. The design makes use of reversible fault tolerant Fredkin gates only. The implementation strategy is to reduce the number of levels of delay there by increasing the speed, which is the most important factor for high speed circuits.

Performance Analysis of Reversible Fast Decimal Adders

This paper presents a performance analysis of reversible, fault tolerant VLSI implementations of carry select and hybrid decimal adders suitable for multi-digit BCD addition. The designs enable partial parallel processing of all digits that perform high-speed addition in decimal domain. When the number of digits is more than 25 the hybrid decimal adder can operate 5 times faster than conventional decimal adder using classical logic gates. The speed up factor of hybrid adder increases above 10 when the number of decimal digits is more than 25 for reversible logic implementation. Such highspeed decimal adders find applications in real time processors and internet-based applications. The implementations use only reversible conservative Fredkin gates, which make it suitable for VLSI circuits.