Design, Fabrication and Characterization of Passive and Active Polymer Photonic Devices

The rapid developments in fields such as fibre optic communication engineering and integrated optical electronics have expanded the interest and have increased the expectations about guided wave optics, in which optical waveguides and optical fibres play a central role. The technology of guided wave photonics now plays a role in generating information (guided-wave sensors) and processing information (spectral analysis, analog-to-digital conversion and other optical communication schemes) in addition to its original application of transmitting information (fibre optic communication). Passive and active polymer devices have generated much research interest recently because of the versatility of the fabrication techniques and the potential applications in two important areas – short distant communication network and special functionality optical devices such as amplifiers, switches and sensors. Polymer optical waveguides and fibres are often designed to have large cores with 10-1000 micrometer diameter to facilitate easy connection and splicing. Large diameter polymer optical fibres being less fragile and vastly easier to work with than glass fibres, are attractive in sensing applications. Sensors using commercial plastic optical fibres are based on ideas already used in silica glass sensors, but exploiting the flexible and cost effective nature of the plastic optical fibre for harsh environments and throw-away sensors. In the field of Photonics, considerable attention is centering on the use of polymer waveguides and fibres, as they have a great potential to create all-optical devices. By attaching organic dyes to the polymer system we can incorporate a variety of optical functions. Organic dye doped polymer waveguides and fibres are potential candidates for solid state gain media. High power and high gain optical amplification in organic dye-doped polymer waveguide amplifier is possible due to extremely large emission cross sections of dyes. Also, an extensive choice of organic dye dopants is possible resulting in amplification covering a wide range in the visible region.

Novel Reactions of TRIS(2-Thienyl)Methane and TRIS(2-Furyal)Methane

A systematic investigation of the reactivity and functionalization of two heterocyclic analogs of triphenylmethane , namely tris(2-thienyl)methane and tris(2-furyl)methane have been carried out and the results are presented in this thesis entitled "NOVEL REACTIONS OF TRIS(2-THIENYL)METHANE AND TRIS(2-FURYL)METHANE.". The history of organic free radicals dates back to Gomberg's monumental discovery of the triphenylmethyl radical in 1900. The heterocyclic analogs of triarylmethane are also interesting from the vantage point of their transformation to the corresponding radicals akin to Gomberg ' s triphenylmethyl radical and also they are prone to further transformation leading to three dimensionally elongated molecules such as dendrimers. Dendritic architectures are one of the most pervasive topologies observed in nature at the macro- and microdimensional length devices. Because of their ability to combine both organic and inorganic compounds and their propensity to either encapsulate or be engineered into unimolecular functional devices , dendrimers are versatile amongst existing nanoscale building blocks and materials.

Design Techniques for Sigmadelta based ADC for Wireless Applications

Analog-to digital Converters (ADC) have an important impact on the overall performance of signal processing system. This research is to explore efficient techniques for the design of sigma-delta ADC,specially for multi-standard wireless tranceivers. In particular, the aim is to develop novel models and algorithms to address this problem and to implement software tools which are avle to assist the designer's decisions in the system-level exploration phase. To this end, this thesis presents a framework of techniques to design sigma-delta analog to digital converters.A2-2-2 reconfigurable sigma-delta modulator is proposed which can meet the design specifications of the three wireless communication standards namely GSM,WCDMA and WLAN. A sigma-delta modulator design tool is developed using the Graphical User Interface Development Environment (GUIDE) In MATLAB.Genetic Algorithm(GA) based search method is introduced to find the optimum value of the scaling coefficients and to maximize the dynamic range in a sigma-delta modulator.

Bidirectional communication using delay coupled chaotic directly modulated semiconductor lasers

Chaotic synchronization of two directly modulated semiconductor lasers with negative delayed optoelectronic feedback is investigated and this scheme is found to be useful for e±cient bidirectional communication between the lasers. A symmetric bidirec- tional coupling is identified as a suitable method for isochronal synchronization of such lasers. The optimum values of coupling and feedback strength that can provide maxi- mum quality of synchronization are identified. This method is successfully employed for encoding/decoding both analog and digital messages. The importance of a symmetric coupling is demonstrated by studying the variation of decoding efficiency with respect to asymmetric coupling.

Multi-user bidirectional communication using isochronal synchronisation of array of chaotic directly modulated semiconductor lasers

Isochronal synchronisation between the elements of an array of three mutually coupled directly modulated semiconductor lasers is utilized for the purpose of simultaneous bidirectional secure communication. Chaotic synchronisation is achieved by adding the coupling signal to the self feedback signal provided to each element of the array. A symmetric coupling is effective in inducing synchronisation between the elements of the array. This coupling scheme provides a direct link between every pair of elements thus making the method suitable for simultaneous bidirectional communication between them. Both analog and digital messages are successfully encrypted and decrypted simultaneously by each element of the array.

Efficient Transmitter/Receiver Architectures for High Performance Wireless Applications

The thesis focuses on efficient design methods and reconfiguration architectures suitable for higher performance wireless communication .The work presented in this thesis describes the development of compact,inexpensive and low power communication devices that are robust,testable and capable of handling multiple communication standards.A new multistandard Decimation Filter Design Toolbox is developed in MATLAB GUIDE environment.RNS based dual-mode decimation filters reconfigurable for WCDMA/WiMAX and WCDMA/WLANa standards are designed and implemented.It offers high speed operation with lesser area requirement and lower dynamic power dissipation.A novel sigma-delta based direct analog-to-residue converter that reduces the complexity of RNS conversion circuitry is presented.The performance of an OFDM communication system with a new RRNS-convolutional concatenated coding is analysed and improved BER performance is obtained under different channel conditions. Easily testable MAC units for filters are presented using Reed-Muller logic for realization.

Design and synthesis of efficient mac architectures for high speed decimal processor

Most of the commercial and financial data are stored in decimal fonn. Recently, support for decimal arithmetic has received increased attention due to the growing importance in financial analysis, banking, tax calculation, currency conversion, insurance, telephone billing and accounting. Performing decimal arithmetic with systems that do not support decimal computations may give a result with representation error, conversion error, and/or rounding error. In this world of precision, such errors are no more tolerable. The errors can be eliminated and better accuracy can be achieved if decimal computations are done using Decimal Floating Point (DFP) units. But the floating-point arithmetic units in today's general-purpose microprocessors are based on the binary number system, and the decimal computations are done using binary arithmetic. Only few common decimal numbers can be exactly represented in Binary Floating Point (BF P). ln many; cases, the law requires that results generated from financial calculations performed on a computer should exactly match with manual calculations. Currently many applications involving fractional decimal data perform decimal computations either in software or with a combination of software and hardware. The performance can be dramatically improved by complete hardware DFP units and this leads to the design of processors that include DF P hardware.VLSI implementations using same modular building blocks can decrease system design and manufacturing cost. A multiplexer realization is a natural choice from the viewpoint of cost and speed.This thesis focuses on the design and synthesis of efficient decimal MAC (Multiply ACeumulate) architecture for high speed decimal processors based on IEEE Standard for Floating-point Arithmetic (IEEE 754-2008). The research goal is to design and synthesize deeimal'MAC architectures to achieve higher performance.Efficient design methods and architectures are developed for a high performance DFP MAC unit as part of this research.

MS Measurements

RMS measuring device is a nonlinear device consisting of linear and nonlinear devices. The performance of rms measurement is influenced by a number of factors; i) signal characteristics, 2) the measurement technique used and 3) the device characteristics. RMS measurement is not simple, particularly when the signals are complex and unknown. The problem of rms measurement on high crest-factor signals is fully discussed and a solution to this problem is presented in this thesis. The problem of rms measurement is systematically analized and found to have mainly three types of errors: (1) amplitude or waveform error 2) Frequency error and (3) averaging error. Various rms measurement techniques are studied and compared. On the basis of this study the rms -measurement is reclassified three categories: (1) Wave-form-error-free measurement (2) High-frequncy-error measurement and (3) Low-frequency error-free measurement. In modern digital sampled-data systems the signals are complex and waveform-error-free rms measurement is highly appreciated. Among the three basic blocks of rms measuring device the squarer is the most important one. A squaring technique is selected, that permits shaping of the squarer error characteristic in such a way as to achieve waveform-errob free rms measurement. The squarer is designed, fabricated and tested. A hybrid rms measurement using an analog rms computing device and digital display combines the speed of analog techniques and the resolution and ease of measurement of digital techniques. An A/D converter is modified to perform the square-rooting operation. A 10-V rms voltmeter using the developed rms detector is fabricated and tested. The chapters two, three and four analyse the problems involved in rms measurement and present a comparative study of rms computing techniques and devices. The fifth chapter gives the details of the developed rms detector that permits wave-form-error free rms measurement. The sixth chapter, enumerates the the highlights of the thesis and suggests a list of future projects

Speaker identification using models for phonemes

Motivation for Speaker recognition work is presented in the first part of the thesis. An exhaustive survey of past work in this field is also presented. A low cost system not including complex computation has been chosen for implementation. Towards achieving this a PC based system is designed and developed. A front end analog to digital convertor (12 bit) is built and interfaced to a PC. Software to control the ADC and to perform various analytical functions including feature vector evaluation is developed. It is shown that a fixed set of phrases incorporating evenly balanced phonemes is aptly suited for the speaker recognition work at hand. A set of phrases are chosen for recognition. Two new methods are adopted for the feature evaluation. Some new measurements involving a symmetry check method for pitch period detection and ACE‘ are used as featured. Arguments are provided to show the need for a new model for speech production. Starting from heuristic, a knowledge based (KB) speech production model is presented. In this model, a KB provides impulses to a voice producing mechanism and constant correction is applied via a feedback path. It is this correction that differs from speaker to speaker. Methods of defining measurable parameters for use as features are described. Algorithms for speaker recognition are developed and implemented. Two methods are presented. The first is based on the model postulated. Here the entropy on the utterance of a phoneme is evaluated. The transitions of voiced regions are used as speaker dependent features. The second method presented uses features found in other works, but evaluated differently. A knock—out scheme is used to provide the weightage values for the selection of features. Results of implementation are presented which show on an average of 80% recognition. It is also shown that if there are long gaps between sessions, the performance deteriorates and is speaker dependent. Cross recognition percentages are also presented and this in the worst case rises to 30% while the best case is 0%. Suggestions for further work are given in the concluding chapter.

Polyphase Implementation of Non-recursive Comb Decimators for Sigma-Delta A/D Converters

In a sigma-delta analog to digital (A/D) As most of the sigma-delta ADC applications require converter, the most computationally intensive block is decimation filters with linear phase characteristics, the decimation filter and its hardware implementation symmetric Finite Impulse Response (FIR) filters are may require millions of transistors. Since these widely used for implementation. But the number of FIR converters are now targeted for a portable application, filter coefficients will be quite large for implementing a a hardware efficient design is an implicit requirement. narrow band decimation filter. Implementing decimation In this effect, this paper presents a computationally filter in several stages reduces the total number of filter efficient polyphase implementation of non-recursive coefficients, and hence reduces the hardware complexity cascaded integrator comb (CIC) decimators for and power consumption [2]. Sigma-Delta Converters (SDCs). The SDCs are The first stage of decimation filter can be operating at high oversampling frequencies and hence implemented very efficiently using a cascade of integrators require large sampling rate conversions. The filtering and comb filters which do not require multiplication or and rate reduction are performed in several stages to coefficient storage. The remaining filtering is performed reduce hardware complexity and power dissipation. either in single stage or in two stages with more complex The CIC filters are widely adopted as the first stage of FIR or infinite impulse response (IIR) filters according to decimation due to its multiplier free structure. In this the requirements. The amount of passband aliasing or research, the performance of polyphase structure is imaging error can be brought within prescribed bounds by compared with the CICs using recursive and increasing the number of stages in the CIC filter. The non-recursive algorithms in terms of power, speed and width of the passband and the frequency characteristics area. This polyphase implementation offers high speed outside the passband are severely limited. So, CIC filters operation and low power consumption. The polyphase are used to make the transition between high and low implementation of 4th order CIC filter with a sampling rates. Conventional filters operating at low decimation factor of '64' and input word length of sampling rate are used to attain the required transition '4-bits' offers about 70% and 37% of power saving bandwidth and stopband attenuation. compared to the corresponding recursive and Several papers are available in literature that deals non-recursive implementations respectively. The same with different implementations of decimation filter polyphase CIC filter can operate about 7 times faster architecture for sigma-delta ADCs. Hogenauer has than the recursive and about 3.7 times faster than the described the design procedures for decimation and non-recursive CIC filters.

Decimal Multiplication using compact BCD Multiplier

Decimal multiplication is an integral part offinancial, commercial, and internet-based computations. The basic building block of a decimal multiplier is a single digit multiplier. It accepts two Binary Coded Decimal (BCD) inputs and gives a product in the range [0, 81] represented by two BCD digits. A novel design for single digit decimal multiplication that reduces the critical path delay and area is proposed in this research. Out of the possible 256 combinations for the 8-bit input, only hundred combinations are valid BCD inputs. In the hundred valid combinations only four combinations require 4 x 4 multiplication, combinations need x multiplication, and the remaining combinations use either x or x 3 multiplication. The proposed design makes use of this property. This design leads to more regular VLSI implementation, and does not require special registers for storing easy multiples. This is a fully parallel multiplier utilizing only combinational logic, and is extended to a Hex/Decimal multiplier that gives either a decimal output or a binary output. The accumulation ofpartial products generated using single digit multipliers is done by an array of multi-operand BCD adders for an (n-digit x n-digit) multiplication.

Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

High performance, low latency double digit decimal multiplier on ASIC and FPGA

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.

Fixed Point Decimal Multiplication Using RPS Algorithm

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. A novel design for single digit decimal multiplication that reduces the critical path delay and area for an iterative multiplier is proposed in this research. The partial products are generated using single digit multipliers, and are accumulated based on a novel RPS algorithm. This design uses n single digit multipliers for an n × n multiplication. The latency for the multiplication of two n-digit Binary Coded Decimal (BCD) operands is (n + 1) cycles and a new multiplication can begin every n cycle. The accumulation of final partial products and the first iteration of partial product generation for next set of inputs are done simultaneously. This iterative decimal multiplier offers low latency and high throughput, and can be extended for decimal floating-point multiplication.

Ethernet Telemetry for Towed Arrays

The towed array electronics is essentially a multichannel real time data acquisition system. The major challenges involved in it are the simultaneous acquisition of data from multiple channels, telemetry of the data over tow cable (several kilometres in some systems) and synchronization with the onboard receiver for accurate reconstruction. A serial protocol is best suited to transmit the data to onboard electronics since number of wires inside the tow cable is limited. The best transmission medium for data over large distances is the optical fibre. In this a two step approach towards the realization of a reliable telemetry scheme for the sensor data using standard protocols is described. The two schemes are discussed in this paper. The first scheme is for conversion of parallel, time-multiplexed multi-sensor data to Ethernet. Existing towed arrays can be upgraded to ethernet using this scheme. Here the last lap of the transmission is by Ethernet over Fibre. For the next generation of towed arrays it is required to digitize and convert the data to ethernet close to the sensor. This is the second scheme. At the heart of this design is the Analog-to-Ethernet node. In addition to a more reliable interface, this helps in easier fault detection and firmware updates in the field for the towed arrays. The design challenges and considerations for incorporating a network of embedded devices within the array are highlighted