A new look at reversible logic implementation of decimal adder

Reversibility plays a fundamental role when logic gates such as AND, OR, and XOR are not reversible. computations with minimal energy dissipation are considered. Hence, these gates dissipate heat and may reduce the life of In recent years, reversible logic has emerged as one of the most the circuit. So, reversible logic is in demand in power aware important approaches for power optimization with its circuits. application in low power CMOS, quantum computing and A reversible conventional BCD adder was proposed in using conventional reversible gates.

A Sub-block Based Image Retrieval Using Modified Integrated Region Matching.

This paper proposes a content based image retrieval (CBIR) system using the local colour and texture features of selected image sub-blocks and global colour and shape features of the image. The image sub-blocks are roughly identified by segmenting the image into partitions of different configuration, finding the edge density in each partition using edge thresholding, morphological dilation. The colour and texture features of the identified regions are computed from the histograms of the quantized HSV colour space and Gray Level Co- occurrence Matrix (GLCM) respectively. A combined colour and texture feature vector is computed for each region. The shape features are computed from the Edge Histogram Descriptor (EHD). A modified Integrated Region Matching (IRM) algorithm is used for finding the minimum distance between the sub-blocks of the query and target image. Experimental results show that the proposed method provides better retrieving result than retrieval using some of the existing methods

Nitrification in a packed bed bioreactor integrated into amarine recirculating maturation system under different substrate concentrations and flow rates

BACKGROUND: A packed bed bioreactor (PBBR) activated with an indigenous nitrifying bacterial consortia was developed and commercialized for rapid establishment of nitrification in brackish water and marine hatchery systems in the tropics. The present study evaluated nitrification in PBBR integrated into a Penaeus monodon recirculating maturation system under different substrate concentrations and flow rates. RESULTS:Instantnitrificationwasobservedafter integration ofPBBRinto thematuration system.TANandNO2-Nconcentrations were always maintained below0.5 mg L−1 during operation. The TANandNO2-N removalwas significant (P < 0.001) in all the six reactor compartments of the PBBR having the substrates at initial concentrations of 2, 5 and 10 mg L−1. The average volumetric TAN removal rates increased with flow rates from 43.51 (250 L h−1) to 130.44 (2500 L h−1) gTAN m−3 day−1 (P < 0.05). FISH analysis of the biofilms after 70 days of operation gave positive results with probes NSO 190 ((β ammonia oxidizers), NsV 443 (Nitrosospira spp.) NEU (halophilic Nitrosomonas), Ntspa 712 (Phylum Nitrospira) indicating stability of the consortia. CONCLUSION: The PBBR integrated into the P. monodon maturation system exhibited significant nitrification upon operation for 70 days as well as at different substrate concentrations and flow rates. This system can easily be integrated into marine and brackish water aquaculture systems, to establish instantaneous nitrification

Integrated Environment for Launch Vehicle Telemetry Data Management

The telemetry data processing operation intended for a given mission are pre-defined by an onboard telemetry configuration, mission trajectory and overall telemetry methodology have stabilized lately for ISRO vehicles. The given problem on telemetry data processing is reduced through hierarchical problem reduction whereby the sequencing of operations evolves as the control task and operations on data as the function task. The function task Input, Output and execution criteria are captured into tables which are examined by the control task and then schedules when the function task when the criteria is being met.

Catalogue Interfaces of Integrated Library Management Systems (ILMS): Experiences in a Proprietary and Open Source Software

The Central Library of Cochin University of Science and Technology (CUSAT) has been automated by proprietary software (Adlib Library) since 2000. After 11 years, in 2011, the university authorities decided to shift to an open source software (OSS), for integrated library management system (ILMS), Koha for automating the library housekeeping operations. In this context, this study attempts to share the experiences in cataloging with both type of software. The features of the cataloging modules of both the software are analysed on the badis of certain check points. It is found that the cataloging module of Koha is almost in par with that of proven proprietary software that has been in market for the past 25 years. Some suggestions made by this study may be incorporated for the further development and perfection of Koha.

Wideband Low-Distortion Sigma-Delta ADC for WLAN

This work presents a wideband low-distortion sigmadelta analog-to-digital converter (ADC) for Wireless Local Area Network (WLAN) standard. The proposed converter makes use of low-distortion swing suppression SDM architecture which is highly suitable for low oversampling ratios to attain high linearity over a wide bandwidth. The modulator employs a 2-2 cascaded sigma-delta modulator with feedforward path with a single-bit quantizer in the first stage and 4-bit in the second stage. The modulator is designed in TSMC 0.18um CMOS technology and operates at 1.8V supply voltage. Simulation results show that, a peak SNDR of 57dB and a spurious free dynamic range (SFDR) of 66dB is obtained for a 10MHz signal bandwidth, and an oversampling ratio of 8.

A Compiler Integrated Assistance for Optimum Data Allocation in Banked Memory Embedded Processors

Bank switching in embedded processors having partitioned memory architecture results in code size as well as run time overhead. An algorithm and its application to assist the compiler in eliminating the redundant bank switching codes introduced and deciding the optimum data allocation to banked memory is presented in this work. A relation matrix formed for the memory bank state transition corresponding to each bank selection instruction is used for the detection of redundant codes. Data allocation to memory is done by considering all possible permutation of memory banks and combination of data. The compiler output corresponding to each data mapping scheme is subjected to a static machine code analysis which identifies the one with minimum number of bank switching codes. Even though the method is compiler independent, the algorithm utilizes certain architectural features of the target processor. A prototype based on PIC 16F87X microcontrollers is described. This method scales well into larger number of memory blocks and other architectures so that high performance compilers can integrate this technique for efficient code generation. The technique is illustrated with an example