Quadratic Predictor based Differential Encoding and Decoding of Speech Signals

Modeling nonlinear systems using Volterra series is a century old method but practical realizations were hampered by inadequate hardware to handle the increased computational complexity stemming from its use. But interest is renewed recently, in designing and implementing filters which can model much of the polynomial nonlinearities inherent in practical systems. The key advantage in resorting to Volterra power series for this purpose is that nonlinear filters so designed can be made to work in parallel with the existing LTI systems, yielding improved performance. This paper describes the inclusion of a quadratic predictor (with nonlinearity order 2) with a linear predictor in an analog source coding system. Analog coding schemes generally ignore the source generation mechanisms but focuses on high fidelity reconstruction at the receiver. The widely used method of differential pnlse code modulation (DPCM) for speech transmission uses a linear predictor to estimate the next possible value of the input speech signal. But this linear system do not account for the inherent nonlinearities in speech signals arising out of multiple reflections in the vocal tract. So a quadratic predictor is designed and implemented in parallel with the linear predictor to yield improved mean square error performance. The augmented speech coder is tested on speech signals transmitted over an additive white gaussian noise (AWGN) channel.

Wideband Low-Distortion Sigma-Delta ADC for WLAN

This work presents a wideband low-distortion sigmadelta analog-to-digital converter (ADC) for Wireless Local Area Network (WLAN) standard. The proposed converter makes use of low-distortion swing suppression SDM architecture which is highly suitable for low oversampling ratios to attain high linearity over a wide bandwidth. The modulator employs a 2-2 cascaded sigma-delta modulator with feedforward path with a single-bit quantizer in the first stage and 4-bit in the second stage. The modulator is designed in TSMC 0.18um CMOS technology and operates at 1.8V supply voltage. Simulation results show that, a peak SNDR of 57dB and a spurious free dynamic range (SFDR) of 66dB is obtained for a 10MHz signal bandwidth, and an oversampling ratio of 8.