Development and plasticity of locomotor circuits in the zebrafish spinal cord

A fundamental goal in neurobiology is to understand the development and organization of neural circuits that drive behavior. In the embryonic spinal cord, the first motor activity is a slow coiling of the trunk that is sensory-independent and therefore appears to be centrally driven. Embryos later become responsive to sensory stimuli and eventually locomote, behaviors that are shaped by the integration of central patterns and sensory feedback. In this thesis I used a simple vertebrate model, the zebrafish, to investigate in three manners how developing spinal networks control these earliest locomotor behaviors. For the first part of this thesis, I characterized the rapid transition of the spinal cord from a purely electrical circuit to a hybrid network that relies on both chemical and electrical synapses. Using genetics, lesions and pharmacology we identified a transient embryonic behavior preceding swimming, termed double coiling. I used electrophysiology to reveal that spinal motoneurons had glutamate-dependent activity patterns that correlated with double coiling as did a population of descending ipsilateral glutamatergic interneurons that also innervated motoneurons at this time. This work (Knogler et al., Journal of Neuroscience, 2014) suggests that double coiling is a discrete step in the transition of the motor network from an electrically coupled circuit that can only produce simple coils to a spinal network driven by descending chemical neurotransmission that can generate more complex behaviors. In the second part of my thesis, I studied how spinal networks filter sensory information during self-generated movement. In the zebrafish embryo, mechanosensitive sensory neurons fire in response to light touch and excite downstream commissural glutamatergic interneurons to produce a flexion response, but spontaneous coiling does not trigger this reflex. I performed electrophysiological recordings to show that these interneurons received glycinergic inputs during spontaneous fictive coiling that prevented them from firing action potentials. Glycinergic inhibition specifically of these interneurons and not other spinal neurons was due to the expression of a unique glycine receptor subtype that enhanced the inhibitory current. This work (Knogler & Drapeau, Frontiers in Neural Circuits, 2014) suggests that glycinergic signaling onto sensory interneurons acts as a corollary discharge signal for reflex inhibition during movement. v In the final part of my thesis I describe work begun during my masters and completed during my doctoral degree studying how homeostatic plasticity is expressed in vivo at central synapses following chronic changes in network activity. I performed whole-cell recordings from spinal motoneurons to show that excitatory synaptic strength scaled up in response to decreased network activity, in accordance with previous in vitro studies. At the network level, I showed that homeostatic plasticity mechanisms were not necessary to maintain the timing of spinal circuits driving behavior, which appeared to be hardwired in the developing zebrafish. This study (Knogler et al., Journal of Neuroscience, 2010) provided for the first time important in vivo results showing that synaptic patterning is less plastic than synaptic strength during development in the intact animal. In conclusion, the findings presented in this thesis contribute widely to our understanding of the neural circuits underlying simple motor behaviors in the vertebrate spinal cord.

FPGA-based object detection using classification circuits

Dans l'apprentissage machine, la classification est le processus d’assigner une nouvelle observation à une certaine catégorie. Les classifieurs qui mettent en œuvre des algorithmes de classification ont été largement étudié au cours des dernières décennies. Les classifieurs traditionnels sont basés sur des algorithmes tels que le SVM et les réseaux de neurones, et sont généralement exécutés par des logiciels sur CPUs qui fait que le système souffre d’un manque de performance et d’une forte consommation d'énergie. Bien que les GPUs puissent être utilisés pour accélérer le calcul de certains classifieurs, leur grande consommation de puissance empêche la technologie d'être mise en œuvre sur des appareils portables tels que les systèmes embarqués. Pour rendre le système de classification plus léger, les classifieurs devraient être capable de fonctionner sur un système matériel plus compact au lieu d'un groupe de CPUs ou GPUs, et les classifieurs eux-mêmes devraient être optimisés pour ce matériel. Dans ce mémoire, nous explorons la mise en œuvre d'un classifieur novateur sur une plate-forme matérielle à base de FPGA. Le classifieur, conçu par Alain Tapp (Université de Montréal), est basé sur une grande quantité de tables de recherche qui forment des circuits arborescents qui effectuent les tâches de classification. Le FPGA semble être un élément fait sur mesure pour mettre en œuvre ce classifieur avec ses riches ressources de tables de recherche et l'architecture à parallélisme élevé. Notre travail montre que les FPGAs peuvent implémenter plusieurs classifieurs et faire les classification sur des images haute définition à une vitesse très élevée.