IRTOPALATERÄN KEHITTÄMINEN SÄRMÄ- JA PROFILOINTIHAKETUKSEEN

Diplomityön tarkoituksena on kehittää irtopalaterä sahahakkeen valmistukseen. Tutkimuksessa perehdytään lastun irtoamisen perusteisiin ja lastun kulkeutumiseen ulos terältä. Tutkimuksessa keskeisenä osana ovat laboratoriokokeet joissa suurnopeuskameralla kuvaamalla selvitetään lastun kulkeutuminen. Saatujen tulosten perusteella muodostetaan terän toimivuuden kannalta keskeiset suunnitteluperusteet. Tutkimuksen kirjallisessa osuudessa selvitetään lastun muodostuminen ja siihen vaikuttavat tekijät.

Eräällä pelkkahakkurilla tuotetun selluhakkeen laatujakauman hallinta

Tämän diplomityön tarkoituksena on selvittää eräällä pelkkahakkurilla tuotetun selluhakkeen laadun vaihtelua ja laadun hallinnan mahdollisuuksia. Tutkittu laite on Veisto Oy:n suunnittelema ja valmistama HewSaw R200 - pelkkahakkuri. Tutkimuksessa selvitetään sahauksen yhteydessä pelkkahakkurilla tuotettavaan selluhakkeeseen vaikuttavien parametrien: hakkurin pyörimisnopeuden, tukin syöttönopeuden, hakkurin terien vaihtovälin, selluhakkeen palakoon, tukkiluokan, puun lämpötilan ja puulajin välisiä korrelaatioita ja edellä mainittujen tekijöiden vaikutusta tuotettavan hakkeen palakokojakaumaan. Tämä palakokojakauma määrää selluhakkeen laadunmäärityksessä käytettävän, niin sanotun hintakertoimen. Kyseinen hintakerroin määritellään SCAN – CM 40 – standardin mukaisella seulonnalla. Tämä standardi on käytössä laadunmäärityksen perusteena kaikilla pohjoismaisilla sellutehtailla.Tutkimuksen kirjallisessa osuudessa esitellään sahateollisuuden merkittävimmät sahausmenetelmät ja sivuotteiden tuotanto . Seuraavassa osassa käsitellään erikseen selluhaketta sahateollisuuden sivutuotteena ja sen taloudellista merkitystä sahateollisuudessa. Jatkossa keskitytään selluhakkeen tuottamiseen pelkkahakkurilla ja puun työstämiseen liittyviin periaatteisiin.Tutkimuksen kokeellisessa osuudessa tutkittaan, eri sahalaitoksilta otettujen hakenäytteiden perusteella, tärkeimmiksi havaittujen tuotantoparametrien vaikutusta selluhakkeen laatuun ja saantoon. Näytteitä otettiin tutkimuksen kokeellisessa osuudessa yhteensä noin 250 kappaletta. Tutkimuksen tuloksia käsittelevässä osuudessa on annettu malli tutkitulla HewSaw R200 - pelkkahakkurilla tuotetun selluhakkeen laadun ja määrän arvioimiseen.

Repeatability in automatic sorting of curved Norway spruce saw logs

Abstract

LWC-paperin opasiteetin parantaminen

LWC-syväpainopaperilta vaaditaan hyvän ajettavuuden, kiillon ja sileyden ohella hyvää opasiteettia. Tämä on asettanut haasteita LWC-paperin valmistajille paperin neliömassojen laskiessa. Tässä diplomityössä etsittiin keinoja parantaa kevyiden LWC-syväpainolajien opasiteettia heikentämättä oleellisesti muita tärkeitä paperin ominaisuuksia. Tavoitteena oli nostaa CR48-lajin opasiteetti tavoitearvoon 90 %. Työn kirjallisuusosassa perehdyttiin paperin optisten ominaisuuksien teoriaan sekä raaka-aineisiin ja prosessin osiin, joilla on vaikutusta paperin opasiteettiin. Työn kokeellisessa osassa tutkittiin olemassa olevan aineiston perusteella tekijöitä, joilla uskottiin olevan vaikutusta CR48-lajin opasiteettiin. Tutkimuksen ja kirjallisuuden perusteella ajettiin tehdaskoeajoa, joiden avulla pyrittiin parantamaan paperin opasiteettia. CR48-lajin opasiteettitavoite saavutettiin kolmella eri tavalla. Opasiteettitavoite saavutettiin, kun paperin vaaleus säädettiin tavoitearvoon pigmenttivärin avulla tumman hierteen sijasta. Tällöin väripigmentin määrää päällystyspastassa nostettiin 0,01 osaa ja valkaistun hierteen osuus kokonaishierteen määrästä oli 100 %. Vaaleuden säätö pastavärillä oli käytännössä hidasta ja hankalaa. Opasiteettitavoite saavutettiin myös, kun hierre jauhettiin täysin koeterillä. Koeterillä tapahtuva jauhatus oli rajumpaa ja katkovampaa kuin perinteisillä terillä, joten hienoaineen lisääntyminen ja kuidun lyheneminen paransivat paperin opasiteettia, mutta lujuudet huononivat. Lisäksi tavoiteopasiteetti saavutettiin, kun sellun osuutta vähennettiin 8 %-yksikköä. Lujuuden säilymisen kannalta sellun vähennys oli parempi keino opasiteetin parantamiseksi kuin hierteen jauhaminen koeterillä. Koeajojen perusteella pohjapaperin tuhkapitoisuuden nostolla ja hierteen CSF-luvun alentamisella ei ollut vaikutusta paperin opasiteettiin. Lisäksi 100 %:nen koeterillä jauhettu sahahakehierre antoi paperille huonomman opasiteetin kuin hierre, josta puolet oli jauhettu koeterillä ja raaka-aineesta 25 % oli sahahaketta.

On Fault Tolerance Methods for Networks-on-Chip

Technology scaling has proceeded into dimensions in which the reliability of manufactured devices is becoming endangered. The reliability decrease is a consequence of physical limitations, relative increase of variations, and decreasing noise margins, among others. A promising solution for bringing the reliability of circuits back to a desired level is the use of design methods which introduce tolerance against possible faults in an integrated circuit. This thesis studies and presents fault tolerance methods for network-onchip (NoC) which is a design paradigm targeted for very large systems-onchip. In a NoC resources, such as processors and memories, are connected to a communication network; comparable to the Internet. Fault tolerance in such a system can be achieved at many abstraction levels. The thesis studies the origin of faults in modern technologies and explains the classification to transient, intermittent and permanent faults. A survey of fault tolerance methods is presented to demonstrate the diversity of available methods. Networks-on-chip are approached by exploring their main design choices: the selection of a topology, routing protocol, and flow control method. Fault tolerance methods for NoCs are studied at different layers of the OSI reference model. The data link layer provides a reliable communication link over a physical channel. Error control coding is an efficient fault tolerance method especially against transient faults at this abstraction level. Error control coding methods suitable for on-chip communication are studied and their implementations presented. Error control coding loses its effectiveness in the presence of intermittent and permanent faults. Therefore, other solutions against them are presented. The introduction of spare wires and split transmissions are shown to provide good tolerance against intermittent and permanent errors and their combination to error control coding is illustrated. At the network layer positioned above the data link layer, fault tolerance can be achieved with the design of fault tolerant network topologies and routing algorithms. Both of these approaches are presented in the thesis together with realizations in the both categories. The thesis concludes that an optimal fault tolerance solution contains carefully co-designed elements from different abstraction levels

Formal Power Analysis of Systems-on-Chip

The design methods and languages targeted to modern System-on-Chip designs are facing tremendous pressure of the ever-increasing complexity, power, and speed requirements. To estimate any of these three metrics, there is a trade-off between accuracy and abstraction level of detail in which a system under design is analyzed. The more detailed the description, the more accurate the simulation will be, but, on the other hand, the more time consuming it will be. Moreover, a designer wants to make decisions as early as possible in the design flow to avoid costly design backtracking. To answer the challenges posed upon System-on-chip designs, this thesis introduces a formal, power aware framework, its development methods, and methods to constraint and analyze power consumption of the system under design. This thesis discusses on power analysis of synchronous and asynchronous systems not forgetting the communication aspects of these systems. The presented framework is built upon the Timed Action System formalism, which offer an environment to analyze and constraint the functional and temporal behavior of the system at high abstraction level. Furthermore, due to the complexity of System-on-Chip designs, the possibility to abstract unnecessary implementation details at higher abstraction levels is an essential part of the introduced design framework. With the encapsulation and abstraction techniques incorporated with the procedure based communication allows a designer to use the presented power aware framework in modeling these large scale systems. The introduced techniques also enable one to subdivide the development of communication and computation into own tasks. This property is taken into account in the power analysis part as well. Furthermore, the presented framework is developed in a way that it can be used throughout the design project. In other words, a designer is able to model and analyze systems from an abstract specification down to an implementable specification.

Structural development of the harvester head saw unit

The main goal of the thesis was to further develop harvester head saw device to the Finnish forest machine manufacturer. The work was done from the basis of the manufacturer´s current production model and the earlier study from this same subject called: “Development of chain saw for harvester” Tero Kaatrasalo, 2004. The work was focused to improving the serviceability and reliability of the saw device, but design also included adding few beforehand determined new features into the saw unit. This was done to give some added value for the end customer. The work includes analysis of the earlier saw devices and ideations of the improvements for the structure.

On the potential utilisation of sawdust and wood chip screenings

This work is based on the utilisation of sawdust and wood chip screenings for different purposes. A substantial amount of these byproducts are readily available in the Finnish forest industry. A black liquor impregnation study showed that sawdust-like wood material behaves differently from normal chips. Furthermore, the fractionation and removal of the smallest size fractions did not have a significant effect on the impregnation of sawdust-like wood material. Sawdust kraft cooking equipped with an impregnation stage increases the cooking yield and decreases the lignin content of the produced pulp. Impregnation also increases viscosity of the pulp and decreases chlorine dioxide consumption in bleaching. In addition, impregnation increases certain pulp properties after refining. Hydrotropic extraction showed that more lignin can be extracted from hardwood than softwood. However, the particle size had a major influence on the lignin extraction. It was possible to extract more lignin from spruce sawdust than spruce chips. Wood chip screenings are usually combusted to generate energy. They can also be used in the production of kraft pulp, ethanol and chemicals. It is not economical to produce ethanol from wood chip screenings because of the expensive wood material. Instead, they should be used for production of steam and energy, kraft pulp and higher value added chemicals. Bleached sawdust kraft pulp can be used to replace softwood kraft pulp in mechanical pulp based papers because it can improve certain physical properties. It is economically more feasible to use bleached sawdust kraft pulp in stead of softwood kraft pulp, especially when the reinforcement power requirement is moderate.

Modeling and Analysis of Noise and Interconnects for On-Chip Communication Link Design

This thesis considers modeling and analysis of noise and interconnects in onchip communication. Besides transistor count and speed, the capabilities of a modern design are often limited by on-chip communication links. These links typically consist of multiple interconnects that run parallel to each other for long distances between functional or memory blocks. Due to the scaling of technology, the interconnects have considerable electrical parasitics that affect their performance, power dissipation and signal integrity. Furthermore, because of electromagnetic coupling, the interconnects in the link need to be considered as an interacting group instead of as isolated signal paths. There is a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects. For this purpose, a set of analytical models is developed for on-chip data links in this thesis. First, a model is proposed for modeling crosstalk and intersymbol interference. The model takes into account the effects of inductance, initial states and bit sequences. Intersymbol interference is shown to affect crosstalk voltage and propagation delay depending on bus throughput and the amount of inductance. Next, a model is proposed for the switching current of a coupled bus. The model is combined with an existing model to evaluate power supply noise. The model is then applied to reduce both functional crosstalk and power supply noise caused by a bus as a trade-off with time. The proposed reduction method is shown to be effective in reducing long-range crosstalk noise. The effects of process variation on encoded signaling are then modeled. In encoded signaling, the input signals to a bus are encoded using additional signaling circuitry. The proposed model includes variation in both the signaling circuitry and in the wires to calculate the total delay variation of a bus. The model is applied to study level-encoded dual-rail and 1-of-4 signaling. In addition to regular voltage-mode and encoded voltage-mode signaling, current-mode signaling is a promising technique for global communication. A model for energy dissipation in RLC current-mode signaling is proposed in the thesis. The energy is derived separately for the driver, wire and receiver termination.