Potential and Challenges of Analog Reconfigurable Computation in Modern and Future CMOS

In this work, the feasibility of the floating-gate technology in analog computing platforms in a scaled down general-purpose CMOS technology is considered. When the technology is scaled down the performance of analog circuits tends to get worse because the process parameters are optimized for digital transistors and the scaling involves the reduction of supply voltages. Generally, the challenge in analog circuit design is that all salient design metrics such as power, area, bandwidth and accuracy are interrelated. Furthermore, poor flexibility, i.e. lack of reconfigurability, the reuse of IP etc., can be considered the most severe weakness of analog hardware. On this account, digital calibration schemes are often required for improved performance or yield enhancement, whereas high flexibility/reconfigurability can not be easily achieved. Here, it is discussed whether it is possible to work around these obstacles by using floating-gate transistors (FGTs), and analyze problems associated with the practical implementation. FGT technology is attractive because it is electrically programmable and also features a charge-based built-in non-volatile memory. Apart from being ideal for canceling the circuit non-idealities due to process variations, the FGTs can also be used as computational or adaptive elements in analog circuits. The nominal gate oxide thickness in the deep sub-micron (DSM) processes is too thin to support robust charge retention and consequently the FGT becomes leaky. In principle, non-leaky FGTs can be implemented in a scaled down process without any special masks by using “double”-oxide transistors intended for providing devices that operate with higher supply voltages than general purpose devices. However, in practice the technology scaling poses several challenges which are addressed in this thesis. To provide a sufficiently wide-ranging survey, six prototype chips with varying complexity were implemented in four different DSM process nodes and investigated from this perspective. The focus is on non-leaky FGTs, but the presented autozeroing floating-gate amplifier (AFGA) demonstrates that leaky FGTs may also find a use. The simplest test structures contain only a few transistors, whereas the most complex experimental chip is an implementation of a spiking neural network (SNN) which comprises thousands of active and passive devices. More precisely, it is a fully connected (256 FGT synapses) two-layer spiking neural network (SNN), where the adaptive properties of FGT are taken advantage of. A compact realization of Spike Timing Dependent Plasticity (STDP) within the SNN is one of the key contributions of this thesis. Finally, the considerations in this thesis extend beyond CMOS to emerging nanodevices. To this end, one promising emerging nanoscale circuit element - memristor - is reviewed and its applicability for analog processing is considered. Furthermore, it is discussed how the FGT technology can be used to prototype computation paradigms compatible with these emerging two-terminal nanoscale devices in a mature and widely available CMOS technology.

Effects of cage size and obstructed view from cage on use of resting platforms by farmed silver foxes

Selostus: Häkin koon ja häkissä olevien näköesteiden vaikutus tarhattujen hopeakettujen makuuhyllyn käyttöön

Comparison between the use of open and walled platforms by juvenile blue foxes (Alopex lagopus)

Selostus: Näköesteen vaikutus sinikettujen hyllynkäyttöön

Porting a Java library to different platforms

Viime aikoina matkapuhelimet ovat alkaneet tukea Javaa matkapuhelinsovellusten ohjelmointikielenä. Javan perusajatus on, että kerran käännetty sovellus voidaan suorittaa useilla laitealustoilla ilman uudelleenkääntämisen tarvetta. Jotta sovellukset voisivat toimia uudella alustalla, niiden käyttämät kirjastot tulee siirtää uudelle alustalle. Tämä diplomityö tutkii tämänkaltaiseen siirtoprojektiin liittyviä asioita. Diplomityön aikana käyttöliittymäkirjasto siirrettiin olemassa olleelta alustalta kahdelle uudelle alustalle. Toinen uusista alustoista oli vanhan alustan uusi versio, ja toinen oli kokonaan uusi alusta. Ohjelmiston siirtämistä helpottaa jos alkuperäinen ohjelmisto on suunniteltu siirrettävyyttä silmälläpitäen. Varsinaiset ohjelmaan tehtävät muutokset ovat tällöin helppoja tehdä. Hyvälaatuisen lopputuloksen saaminen vaatii kuitenkin aina että ohjelmisto myös testataan huolellisesti.

Smart homes as service platforms. Research report of ÄLYKOP sub-project “Competitive advantage from customer value”

In this report, we summarize results of our part of the ÄLYKOP-project on customer value creation in the intersection of the health care, ICT, forest and energy industries. The research directs to describe how industry transformation and convergence create new possibilities, business opportunities and even new industries.The report consists of findings which are presented former in academic publications. The publication discusses on customer value, service provision and resource basis of the novel concepts through multiple theorethical frameworks. The report is divided into three maim sections which are theoretical background, discussion on health care industry and evaluations regarding novel smart home concepts. Transaction cost economics and Resource- Based view on the firm provides the theoretical basis to analyze the prescribed phenomena. The health care industry analysis describes the most important changes in the demand conditions of health care services, and explores the features that are likely to open new business opportunities for a solution provider. The third part of the report on the smart home business provides illustrations few potential concepts that can be considered to provide solutions to economical problems which arise from aging of population. The results provide several recommendations for the smart home platform developers in public and private sectors. By the analysis, public organizations dominate service provision and private markets are emergent state at present. We argue that public-private partnerships are nececssary for creating key suppliers. Indeed, paying attion on appropriate regulation, service specifications and technology standards would foster diffusion of new services. The dynamics of the service provision networks is driven by need for new capabiltities which are required for adapting business concepts to new competitive situation. Finally, the smart home framework revealed links between conventionally distant business areas such as health care and energy distribution. The platform integrates functionalities different for purposes which however apply same resource basis.

On Energy Efficient Computing Platforms

In accordance with the Moore's law, the increasing number of on-chip integrated transistors has enabled modern computing platforms with not only higher processing power but also more affordable prices. As a result, these platforms, including portable devices, work stations and data centres, are becoming an inevitable part of the human society. However, with the demand for portability and raising cost of power, energy efficiency has emerged to be a major concern for modern computing platforms. As the complexity of on-chip systems increases, Network-on-Chip (NoC) has been proved as an efficient communication architecture which can further improve system performances and scalability while reducing the design cost. Therefore, in this thesis, we study and propose energy optimization approaches based on NoC architecture, with special focuses on the following aspects. As the architectural trend of future computing platforms, 3D systems have many bene ts including higher integration density, smaller footprint, heterogeneous integration, etc. Moreover, 3D technology can signi cantly improve the network communication and effectively avoid long wirings, and therefore, provide higher system performance and energy efficiency. With the dynamic nature of on-chip communication in large scale NoC based systems, run-time system optimization is of crucial importance in order to achieve higher system reliability and essentially energy efficiency. In this thesis, we propose an agent based system design approach where agents are on-chip components which monitor and control system parameters such as supply voltage, operating frequency, etc. With this approach, we have analysed the implementation alternatives for dynamic voltage and frequency scaling and power gating techniques at different granularity, which reduce both dynamic and leakage energy consumption. Topologies, being one of the key factors for NoCs, are also explored for energy saving purpose. A Honeycomb NoC architecture is proposed in this thesis with turn-model based deadlock-free routing algorithms. Our analysis and simulation based evaluation show that Honeycomb NoCs outperform their Mesh based counterparts in terms of network cost, system performance as well as energy efficiency.

Printed platforms for paper-based analytical applications

Paper-based analytical technologies enable quantitative and rapid analysis of analytes from various application areas including healthcare, environmental monitoring and food safety. Because paper is a planar, flexible and light weight substrate, the devices can be transported and disposed easily. Diagnostic devices are especially valuable in resourcelimited environments where diagnosis as well as monitoring of therapy can be made even without electricity by using e.g. colorimetric assays. On the other hand, platforms including printed electrodes can be coupled with hand-held readers. They enable electrochemical detection with improved reliability, sensitivity and selectivity compared with colorimetric assays. In this thesis, different roll-to-roll compatible printing technologies were utilized for the fabrication of low-cost paper-based sensor platforms. The platforms intended for colorimetric assays and microfluidics were fabricated by patterning the paper substrates with hydrophobic vinyl substituted polydimethylsiloxane (PDMS) -based ink. Depending on the barrier properties of the substrate, the ink either penetrates into the paper structure creating e.g. microfluidic channel structures or remains on the surface creating a 2D analog of a microplate. The printed PDMS can be cured by a roll-ro-roll compatible infrared (IR) sintering method. The performance of these platforms was studied by printing glucose oxidase-based ink on the PDMS-free reaction areas. The subsequent application of the glucose analyte changed the colour of the white reaction area to purple with the colour density and intensity depending on the concentration of the glucose solution. Printed electrochemical cell platforms were fabricated on paper substrates with appropriate barrier properties by inkjet-printing metal nanoparticle based inks and by IR sintering them into conducting electrodes. Printed PDMS arrays were used for directing the liquid analyte onto the predetermined spots on the electrodes. Various electrochemical measurements were carried out both with the bare electrodes and electrodes functionalized with e.g. self assembled monolayers. Electrochemical glucose sensor was selected as a proof-of-concept device to demonstrate the potential of the printed electronic platforms.

User-generated experiences: how automated platforms for content creation and sharing has transformed information access

Esitys KDK-käytettävyystyöryhmän järjestämässä seminaarissa: Miten käyttäjien toiveet haastavat metatietokäytäntöjämme? / How users' expectations challenge our metadata practices? 30.9.2014.

Development of agnostic mobile applications with cross-platform cloud computing platforms

Smart phones became part and parcel of our life, where mobility provides a freedom of not being bounded by time and space. In addition, number of smartphones produced each year is skyrocketing. However, this also created discrepancies or fragmentation among devices and OSes, which in turn made an exceeding hard for developers to deliver hundreds of similar featured applications with various versions for the market consumption. This thesis is an attempt to investigate whether cloud based mobile development platforms can mitigate and eventually eliminate fragmentation challenges. During this research, we have selected and analyzed the most popular cloud based development platforms and tested integrated cloud features. This research showed that cloud based mobile development platforms may able to reduce mobile fragmentation and enable to utilize single codebase to deliver a mobile application for different platforms.

Virtual Runtime Application Partitions for Resource Management in Massively Parallel Architectures

This thesis presents a novel design paradigm, called Virtual Runtime Application Partitions (VRAP), to judiciously utilize the on-chip resources. As the dark silicon era approaches, where the power considerations will allow only a fraction chip to be powered on, judicious resource management will become a key consideration in future designs. Most of the works on resource management treat only the physical components (i.e. computation, communication, and memory blocks) as resources and manipulate the component to application mapping to optimize various parameters (e.g. energy efficiency). To further enhance the optimization potential, in addition to the physical resources we propose to manipulate abstract resources (i.e. voltage/frequency operating point, the fault-tolerance strength, the degree of parallelism, and the configuration architecture). The proposed framework (i.e. VRAP) encapsulates methods, algorithms, and hardware blocks to provide each application with the abstract resources tailored to its needs. To test the efficacy of this concept, we have developed three distinct self adaptive environments: (i) Private Operating Environment (POE), (ii) Private Reliability Environment (PRE), and (iii) Private Configuration Environment (PCE) that collectively ensure that each application meets its deadlines using minimal platform resources. In this work several novel architectural enhancements, algorithms and policies are presented to realize the virtual runtime application partitions efficiently. Considering the future design trends, we have chosen Coarse Grained Reconfigurable Architectures (CGRAs) and Network on Chips (NoCs) to test the feasibility of our approach. Specifically, we have chosen Dynamically Reconfigurable Resource Array (DRRA) and McNoC as the representative CGRA and NoC platforms. The proposed techniques are compared and evaluated using a variety of quantitative experiments. Synthesis and simulation results demonstrate VRAP significantly enhances the energy and power efficiency compared to state of the art.

Agent-based management systems for many-core platforms : rigorous design and efficient implementation

Due to various advantages such as flexibility, scalability and updatability, software intensive systems are increasingly embedded in everyday life. The constantly growing number of functions executed by these systems requires a high level of performance from the underlying platform. The main approach to incrementing performance has been the increase of operating frequency of a chip. However, this has led to the problem of power dissipation, which has shifted the focus of research to parallel and distributed computing. Parallel many-core platforms can provide the required level of computational power along with low power consumption. On the one hand, this enables parallel execution of highly intensive applications. With their computational power, these platforms are likely to be used in various application domains: from home use electronics (e.g., video processing) to complex critical control systems. On the other hand, the utilization of the resources has to be efficient in terms of performance and power consumption. However, the high level of on-chip integration results in the increase of the probability of various faults and creation of hotspots leading to thermal problems. Additionally, radiation, which is frequent in space but becomes an issue also at the ground level, can cause transient faults. This can eventually induce a faulty execution of applications. Therefore, it is crucial to develop methods that enable efficient as well as resilient execution of applications. The main objective of the thesis is to propose an approach to design agentbased systems for many-core platforms in a rigorous manner. When designing such a system, we explore and integrate various dynamic reconfiguration mechanisms into agents functionality. The use of these mechanisms enhances resilience of the underlying platform whilst maintaining performance at an acceptable level. The design of the system proceeds according to a formal refinement approach which allows us to ensure correct behaviour of the system with respect to postulated properties. To enable analysis of the proposed system in terms of area overhead as well as performance, we explore an approach, where the developed rigorous models are transformed into a high-level implementation language. Specifically, we investigate methods for deriving fault-free implementations from these models into, e.g., a hardware description language, namely VHDL.

Power and Performance Management Strategies on NoC-Based Multicore Platforms, Using DVFS, Adaptive Algorithm and Task Parallelism

This work presents synopsis of efficient strategies used in power managements for achieving the most economical power and energy consumption in multicore systems, FPGA and NoC Platforms. In this work, a practical approach was taken, in an effort to validate the significance of the proposed Adaptive Power Management Algorithm (APMA), proposed for system developed, for this thesis project. This system comprise arithmetic and logic unit, up and down counters, adder, state machine and multiplexer. The essence of carrying this project firstly, is to develop a system that will be used for this power management project. Secondly, to perform area and power synopsis of the system on these various scalable technology platforms, UMC 90nm nanotechnology 1.2v, UMC 90nm nanotechnology 1.32v and UMC 0.18 μmNanotechnology 1.80v, in order to examine the difference in area and power consumption of the system on the platforms. Thirdly, to explore various strategies that can be used to reducing system’s power consumption and to propose an adaptive power management algorithm that can be used to reduce the power consumption of the system. The strategies introduced in this work comprise Dynamic Voltage Frequency Scaling (DVFS) and task parallelism. After the system development, it was run on FPGA board, basically NoC Platforms and on these various technology platforms UMC 90nm nanotechnology1.2v, UMC 90nm nanotechnology 1.32v and UMC180 nm nanotechnology 1.80v, the system synthesis was successfully accomplished, the simulated result analysis shows that the system meets all functional requirements, the power consumption and the area utilization were recorded and analyzed in chapter 7 of this work. This work extensively reviewed various strategies for managing power consumption which were quantitative research works by many researchers and companies, it's a mixture of study analysis and experimented lab works, it condensed and presents the whole basic concepts of power management strategy from quality technical papers.