Simulation of new p-type pixel strip detector with enhanced multiplication effect

This Master’s Thesis is dedicated to the simulation of new p-type pixel strip detector with enhanced multiplication effect. It is done for high-energy physics experiments upgrade such as Super Large Hadron Collider especially for Compact Muon Solenoid particle track silicon detectors. These detectors are used in very harsh radiation environment and should have good radiation hardness. The device engineering technology for developing more radiation hard particle detectors is used for minimizing the radiation degradation. New detector structure with enhanced multiplication effect is proposed in this work. There are studies of electric field and electric charge distribution of conventional and new p-type detector under reverse voltage bias and irradiation. Finally, the dependence of the anode current from the applied cathode reverse voltage bias under irradiation is obtained in this Thesis. For simulation Silvaco Technology Computer Aided Design software was used. Athena was used for creation of doping profiles and device structures and Atlas was used for getting electrical characteristics of the studied devices. The program codes for this software are represented in Appendixes.

3D Stripixel Detectors Simulation

Solid-state silicon detectors have replaced conventional ones in almost all recent high-energy physics experiments. Pixel silicon sensors don't have any alternative in the area near the interaction point because of their high resolution and fast operation speed. However, present detectors hardly withstand high radiation doses. Forthcoming upgrade of the LHC in 2014 requires development of a new generation of pixel detectors which will be able to operate under ten times increased luminosity. A planar fabrication technique has some physical limitations; an improvement of the radiation hardness will reduce sensitivity of a detector. In that case a 3D pixel detector seems to be the most promising device which can overcome these difficulties. The objective of this work was to model a structure of the 3D stripixel detector and to simulate electrical characteristics of the device. Silvaco Atlas software has been used for these purposes. The structures of single and double sided dual column detectors with active edges were described using special command language. Simulations of these detectors have shown that electric field inside an active area has more uniform distribution in comparison to the planar structure. A smaller interelectrode space leads to a stronger field and also decreases the collection time. This makes the new type of detectors more radiation resistant. Other discovered advantages are the lower full depletion voltage and increased charge collection efficiency. So the 3D stripixel detectors have demonstrated improved characteristics and will be a suitable replacement for the planar ones.

Transient current technique simulation of semiconductor detectors

Nowadays advanced simulation technologies of semiconductor devices occupies an important place in microelectronics production process. Simulation helps to understand devices internal processes physics, detect new effects and find directions for optimization. Computer calculation reduces manufacturing costs and time. Modern simulation suits such as Silcaco TCAD allow simulating not only individual semiconductor structures, but also these structures in the circuit. For that purpose TCAD include MixedMode tool. That tool can simulate circuits using compact circuit models including semiconductor structures with their physical models. In this work, MixedMode is used for simulating transient current technique setup, which include detector and supporting electrical circuit. This technique was developed by RD39 collaboration project for investigation radiation detectors radiation hard properties.

Modeling Front End Electronics for a Gas Electron Multiplier Detector

The Large Hadron Collider (LHC) in The European Organization for Nuclear Research (CERN) will have a Long Shutdown sometime during 2017 or 2018. During this time there will be maintenance and a possibility to install new detectors. After the shutdown the LHC will have a higher luminosity. A promising new type of detector for this high luminosity phase is a Triple-GEM detector. During the shutdown these detectors will be installed at the Compact Muon Solenoid (CMS) experiment. The Triple-GEM detectors are now being developed at CERN and alongside also a readout ASIC chip for the detector. In this thesis a simulation model was developed for the ASICs analog front end. The model will help to carry out more extensive simulations and also simulate the whole chip before the whole design is finished. The proper functioning of the model was tested with simulations, which are also presented in the thesis.

Readout architectures for hybrid pixel detector readout chips

The original contribution of this thesis to knowledge are novel digital readout architectures for hybrid pixel readout chips. The thesis presents asynchronous bus-based architecture, a data-node based column architecture and a network-based pixel matrix architecture for data transportation. It is shown that the data-node architecture achieves readout efficiency 99% with half the output rate as a bus-based system. The network-based solution avoids “broken” columns due to some manufacturing errors, and it distributes internal data traffic more evenly across the pixel matrix than column-based architectures. An improvement of > 10% to the efficiency is achieved with uniform and non-uniform hit occupancies. Architectural design has been done using transaction level modeling (TLM) and sequential high-level design techniques for reducing the design and simulation time. It has been possible to simulate tens of column and full chip architectures using the high-level techniques. A decrease of > 10 in run-time is observed using these techniques compared to register transfer level (RTL) design technique. Reduction of 50% for lines-of-code (LoC) for the high-level models compared to the RTL description has been achieved. Two architectures are then demonstrated in two hybrid pixel readout chips. The first chip, Timepix3 has been designed for the Medipix3 collaboration. According to the measurements, it consumes < 1 W/cm^2. It also delivers up to 40 Mhits/s/cm^2 with 10-bit time-over-threshold (ToT) and 18-bit time-of-arrival (ToA) of 1.5625 ns. The chip uses a token-arbitrated, asynchronous two-phase handshake column bus for internal data transfer. It has also been successfully used in a multi-chip particle tracking telescope. The second chip, VeloPix, is a readout chip being designed for the upgrade of Vertex Locator (VELO) of the LHCb experiment at CERN. Based on the simulations, it consumes < 1.5 W/cm^2 while delivering up to 320 Mpackets/s/cm^2, each packet containing up to 8 pixels. VeloPix uses a node-based data fabric for achieving throughput of 13.3 Mpackets/s from the column to the EoC. By combining Monte Carlo physics data with high-level simulations, it has been demonstrated that the architecture meets requirements of the VELO (260 Mpackets/s/cm^2 with efficiency of 99%).

A game theoretic simulation model for quality oriented timber supply to sawmills

Summary

Comparison of thinning methods in a Scots pine stand on drained peatland : a simulation study

Tiivistelmä: Harvennusmenetelmien vertailu ojitetun turvemaan männikössä. Simulointitutkimus

Comparing simulation methods for modelling the errors of stand inventory data

Abstract